Description
The Abdus Salam International Centre for Theoretical Physics (ICTP, Italy) and the University Kebangsaan Malaysia (UKM, Malaysia) will jointly organize the Asian Regional Conference and Workshop on Advanced Reconfigurable Instrumentation for Scientific Applications, to be held at the UKM, Bangi, Selangor, Malaysia, from 14 to 25 November 2016.
The first three days of the activity will be dedicated to the 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEESE 2016) to be held at Putrajaya Marriot Hotel, Putrajaya, Malaysia, from 14 to 16 November 2016.  The theme of the conference is "Technologies for Society's Well-being". Prof. Kajita Takaaki, 2015 Nobel Prize in Physics, and Prof. Fernando Quevedo, Director of ICTP, will be Keynote Speakers at the Conference. Specific information about the Conference can be found at http://www.icaeese2016.org/
 
BRIEF DESCRIPTION OF THE WORKSHOP
This Workshop is mainly intended as a training activity on modern FPGA-based Programmable System-on-Chip (SoC) with emphasis on scientific and academic applications. The purpose of the Workshop is to provide key know-how for the implementation of complete digital systems using low-cost high-performance reconfigurable hardware platforms.  New generation of SoC technology relays on embedded processing based on the combination of general purpose processors with traditional FPGA integrated in a single chip. This means that the processor and the FPGA can be complementary used for what they do best, achieving unprecedented performance.
The main topics of the Workshop will include the fundamentals of:
  • Modern Digital Design and Digital Arithmetic
  • FPGA and VHDL for Modeling, Simulation and Logic Synthesis
  • Embedded C Language Programming and Dual-Core ARM Cortex Processor
  • SoC Design Methodology
  • Advanced SoC Trends
  • Hands-on Training and Experimentation
 
Scientists, technologists, teachers and students from South and Southeast Asian countries may apply for participation. 
 
GRANTS
A limited number of grants are available to support the travel and living expenses of selected participants, with priority given to participants working in a developing country and who are at the early stages of their career.
There is no registration fee to attend the Workshop.
Selected participants of the Workshop will automatically enjoy the waiver of the ICAEESE 2016 registration fees.
Go to day
  • Thursday, 17 November 2016
    • 09:00 - 18:30 Thursday, 17 November 2016
      • 09:00 Opening 1h0'
        Speaker: Directors and Organizers
      • 10:00 Essentials of Digital Design 1h0'
        Speaker: Pirouz BAZARGAN-SABET (University Pierre & Marie Curie, Paris, France)
      • 11:00 Coffee Break 30'
      • 11:30 Essentials of Digital Design 1h0'
        Speaker: Pirouz BAZARGAN-SABET, (University Pierre & Marie Curie, Paris, France)
      • 12:30 Lunch break 1h30'
      • 14:00 SoC-FPGA Fundamentals 2h0'
        Speaker: Nizar ABDALLAH (Microsemi, Mountain View, CA, USA)
      • 16:00 Coffee break 30'
      • 16:30 SoC Design Methodology 1h0'
        Speaker: Julio DONDO (Universidad de Castilla-La Mancha, Spain)
      • 17:30 Vivado Design Suite Process 1h0'
        Speaker: Julio DONDO (Universidad de Castilla-La Mancha, Spain)
  • Friday, 18 November 2016
    • 09:00 - 18:30 Friday, 18 November 2016
      • 09:00 Modern Digital Arithmetic 2h0'
        Speaker: Pirouz BAZARGAN-SABET (University Pierre & Marie Curie, Paris, France)
      • 11:00 Coffee break 30'
      • 11:30 Advanced SoC-FPGA Trends 1h0'
        Speaker: Nizar ABDALLAH (Microsemi, Mountain View, CA, USA)
      • 12:30 Lunch break 1h30'
      • 14:00 Advanced SoC-FPGA Trends 2h0'
        Speaker: Nizar ABDALLAH (Microsemi, Mountain View, CA, USA)
      • 16:00 Coffee break 30'
      • 16:30 Introduction to Zynq Architecture 1h0'
        Speaker: Julio DONDO (Universidad de Castilla-La Mancha, Spain)
      • 17:30 Demo on Zedboard 1h0'
        Speaker: Julio DONDO (Universidad de Castilla-La Mancha, Spain)
  • Monday, 21 November 2016
    • 09:00 - 18:30 Monday, 21 November 2016
      • 09:00 VHDL for Implementing Digital Systems into FPGAs 2h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 11:00 Coffee break 30'
      • 11:30 VHDL for Implementing Digital Systems into FPGAs 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 12:30 Lunch break 1h30'
      • 14:00 SoC design based on Zynq device. Programmable Logic (PL) 2h0'
        Speaker: Tayab Din Memon (Mehran University of Engineering and Technology MUET, Jamshoro, Pakistan)
      • 16:00 Coffee break 30'
      • 16:30 Zinq design. Programmable Logic. (Lab Tutorial) 2h0'
        Speakers: Tayab Din Memon (Mehran University of Engineering and Technology MUET, Jamshoro, Pakistan), Kasun Sameera Mannatunga (University of Moratuwa, Sri Lanka)
  • Tuesday, 22 November 2016
    • 09:00 - 18:30 Tuesday, 22 November 2016
      • 09:00 Programmable SoC Architecture 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 10:00 Zynq Architecture: Processing System and Programmable Logic 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 11:00 Coffee break 30'
      • 11:30 Zynq Architecture: Processing System and Programmable Logic 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 12:30 Lunch break 1h30'
      • 14:00 Introduction to AXI Interface 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 15:00 Serial communication interface with FPGA 1h0'
        Speaker: Thulasiraman Nandha Kumar (The University of Nottingham, Malaysia Campus, Selangor, Malaysia)
      • 16:00 Coffee break 30'
      • 16:30 Serial communication interface with FPGA 2h0'
        Speaker: Thulasiraman NANDHA KUMAR (The University of Nottingham, Malaysia Campus, Selangor, Malaysia)
  • Wednesday, 23 November 2016
    • 09:00 - 18:30 Wednesday, 23 November 2016
      • 09:00 Embedded System Design 2h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 11:00 Coffee break 30'
      • 11:30 Embedded C in Zynq 1h0'
        Speaker: Maria Liz CRESPO (ICTP, Trieste, Italy)
      • 12:30 Lunch break 1h30'
      • 14:00 Zynq design. Processing System (PS) 2h0'
        Speaker: Kasun Saneera MANNATUNGA (University of Moratuwa, Moratuwa, Sri Lanka)
      • 16:00 Coffee break 30'
      • 16:30 Zinq design. Processing System. Memory test. (Lab Tutorial) 2h0'
        Speakers: Kasun Saneera MANNATUNGA (University of Moratuwa, Moratuwa, Sri Lanka), Tayab Din Memon (Mehran University of Engineering and Technology MUET, Jamshoro, Pakistan)
  • Thursday, 24 November 2016
    • 09:00 - 18:30 Thursday, 24 November 2016
      • 09:00 Timers and Interruptions 2h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 11:00 Coffee break 30'
      • 11:30 ZedBoard System Architecture 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 12:30 Lunch break 1h30'
      • 14:00 Zynq design using GPIO IP Cores in PL 2h0'
        Speaker: Kasun Saneera MANNATUNGA (University of Moratuwa, Moratuwa, Sri Lanka)
      • 16:00 Coffee break 30'
      • 16:30 Zynq design using GPIO IP Cores in PL (Lab Tutorial) 2h0'
        Speakers: Kasun Saneera MANNATUNGA (University of Moratuwa, Moratuwa, Sri Lanka), Tayab Din Memon (Mehran University of Engineering and Technology MUET, Jamshoro, Pakistan)
  • Friday, 25 November 2016
    • 09:00 - 18:30 Friday, 25 November 2016
      • 09:00 Zedboard Interface 2h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
      • 11:00 Coffee break 30'
      • 11:30 PyQT Design Example with Ethernet Communication 1h0'
        Speaker: Maria Liz CRESPO (ICTP, Trieste, Italy)
      • 12:30 Lunch break 1h30'
      • 14:00 PyQT Design Example with Ethernet Communication 2h0'
        Speaker: Maria Liz CRESPO (ICTP, Trieste, Italy)
      • 16:00 Coffee break 30'
      • 16:30 Distribution of certificates 2h0'