Scientific Calendar Event



Description Description:

The workshop will focus on the applicability of modern FPGA-based technology for scientific computing, including a review of present state of the art, technical challenges, and opportunities for supercomputing of scientific interest with particular emphasis on non-von Neumann architectures.

FPGA-based devices are characterized by its low-cost along with a huge versatility to implement different concurrent tasks and critical activities such as hard real-time data acquisition, processing and transmission. These features make these devices very attractive for frontier scientific applications. The workshop will provide a thoroughly review of present state of the art of FPGA-based architectures and design methodologies with emphasis on high performance computational applications.

The workshop will consist of about 65 hours of theoretical lectures and assisted hands-on activities. The selected faculty will be composed by lecturers from prestigious universities, hi-tech companies and research institutions.
The workshop will be primarily addressed to researchers, teachers and advanced students who need to master modern FPGA-based technologies for their scientific and academic activities.

Topics:
 
  • Modern FPGA architectures and their hybrid versions with embedded RISC processors.
  • Design methodologies, hardware description languages, and synthesis tools.
  • High level languages and high level synthesis.
  • Real Time operating systems.
  • Fine-grained reconfigurable computing.
  • FPGA-based Systems-on-Chip: design for scalability and portability
  • Physical implementation, optimization, and FPGA debugging techniques
  • The workshop will include experimental sessions with hardware development platforms and software design tools. It will be also explored possible interdisciplinary collaborations.
Grants:

A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee.

Go to day
  • Monday, 13 May 2019
    • 08:30 - 11:30
      • 08:30 Registration and Administrative formalities 2h30'
        REGISTRATION: Upon arrival, Visitors not staying in the ICTP Guest Houses, are kindly requested  to complete registration formalities at the Adriatico Guesthouse as follows: Office 3(Lower level) from 8.30 till 11.00.
        
        TRAVEL UNIT (Only for those Visitors receiving daily living allowance/travel reimbursement, who  have not provided their bank account data through the on-line portal)  
        Only after having completed registration formalities, please go to the Travel Unit, EF, Main Entrance, Room T17, ground floor, open two days:  Monday and Friday, 08.30 - 12.00  and 13.30 - 14.30
        Please bring with you: badge/identity card or passport/any travel tickets and boarding passes, if reimbursement due.
      • 11:00 Coffee break 30'
    • 11:30 - 14:00 Opening
      • 11:30 Welcome to the Workshop 20'
        Speaker: Sandro SCANDOLO (ICTP), Andres CICUTTIN (ICTP), Maria Liz CRESPO (ICTP)
      • 11:50 Workshop Outline 20'
        Speaker: Maria Liz CRESPO (ICTP)
        Material: Slides
      • 12:10 Brief introduction from participants 20'
      • 12:30 Lunch break 1h30'
    • 14:00 - 17:30
      • 14:00 All-Programmable System-on-Chip (SoC) technology 1h30'
        Speaker: Cristian SISTERNA (UNSJ, Argentina)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 The SoC Architecture and Design Methodology 1h30'
        Speaker: Cristian SISTERNA (UNSJ, Argentina)
        Material: Slides
  • Tuesday, 14 May 2019
    • 09:00 - 18:30
      • 09:00 The JANUS project 1h30'
        Speaker: Sebastiano Fabio SCHIFANO (Janus, University of Ferrara)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 EuroEXA project and FPGAs 1h30'
        Speaker: Enrico CALORE (Janus, University of Ferrara)
        Material: Slides
      • 12:30 Lunch break 1h30'
      • 14:00 Digital arithmetic and numerical representations 1h30'
        Speaker: Pirouz BAZARGAN SABET (LIP6, Paris, France)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 Evaluation and Development Board (Zedboard) 1h30'
        Speaker: Cristian SISTERNA (UNSJ, Argentina)
        Material: Slides
      • 17:30 Lab activities with tutors: Design flow based on the processing system 1h0'
    • 19:30 - 20:30
      Location: Adriatico GuestHouse - Cafeteria
      • 19:30 Welcome Reception 1h0'
        All participants are cordially invited to the Welcome Reception.
  • Wednesday, 15 May 2019
    • 09:00 - 18:30
      • 09:00 Floating point operators: Square Root and Division 1h30'
        Speaker: Pirouz BAZARGAN SABET (LIP6, Paris, France)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 The Era of All Programmable SoC: challenges for supercomputing 1h30'
        Speaker: Nizar ABDALLAH (Microsemi, San Diego, USA)
        Material: Slides
      • 12:30 Lunch break 1h30'
      • 14:00 C for Embedded Systems 1h30'
        Speaker: Cristian SISTERNA (UNSJ, Argentina)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 Lab Tutorial: Building a complete Embedded System 1h0'
        Speaker: Romina MOLINA (UNSL, Argentina)
      • 17:00 Lab activities with tutors 1h30'
  • Thursday, 16 May 2019
    • 09:00 - 18:30
      • 09:00 BondMachine, a mouldable computer architecture 1h30'
        Speaker: Mirko MARIOTTI (University of Perugia, Perugia)
        Material: A script to configure the material Slides The hands-on Material Updated documentation
      • 10:30 Coffee break 20'
      • 10:50 Group Picture 10'
      • 11:00 BondMachine, a mouldable computer architecture (cont.) 1h30'
        Speaker: Mirko MARIOTTI (University of Perugia, Perugia)
      • 12:30 Lunch break 1h30'
      • 14:00 AXI Custom IP 1h30'
        Speaker: Cristian SISTERNA (UNSJ, Argentina)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 Lab Tutorial: Custom AXI IP Core 1h0'
        Speaker: Luis Garcia ORDONEZ (ICTP / Guatemala)
      • 17:00 Lab activities with tutors 1h30'
  • Friday, 17 May 2019
    • 09:00 - 18:30
      • 09:00 The RISK V architecture 1h30'
        Speaker: Nizar ABDALLAH (Microsemi, San Diego, USA)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 The RISK V architecture (cont.) 1h30'
        Speaker: Nizar ABDALLAH (Microsemi, San Diego, USA)
      • 12:30 Lunch break 1h30'
      • 14:00 From Advanced Instrumentation Towards Supercomputing 1h30'
        Speaker: Andres CICUTTIN (ICTP)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 Lab Tutorial: Data transfer with DMA 1h0'
        Speaker: Rodrigo MELO (INTI, Argentina)
      • 17:00 Lab activities with tutors 1h30'
  • Monday, 20 May 2019
    • 09:00 - 18:30
      • 09:00 FreeRTOS operating system for SoC 1h30'
        Speaker: Fernando RINCON CALLE (UCLM, Spain)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 TCP/IP communication: The LwIP library 1h30'
        Speaker: Fernando RINCON CALLE (UCLM, Spain)
        Material: Slides
      • 12:30 Lunch break 1h30'
      • 14:00 Lab Tutorial: FPGA-Processor Interface 1h30'
        Speaker: Rodrigo MELO (INTI, Argentina)
      • 15:30 Coffee break 30'
      • 16:00 Lab activities with tutors 2h30'
  • Tuesday, 21 May 2019
    • 09:00 - 18:30
      • 09:00 Lab Tutorial: First steps with FreeRTOS & LwIP library 1h30'
        Speaker: Fernando RINCON CALLE (UCLM, Spain)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 Front-Ends and DAQ for Particle Physics experiments 45'
        Speaker: Igor KONOROV (TUM, Munich)
        Material: Slides
      • 11:45 The new generation of Intelligent FPGA based DAQ architectures 45'
        Speaker: Igor KONOROV (TUM, Munich)
      • 12:30 Lunch break 1h30'
      • 14:00 Lab. Tutorial: How to access the SoC from a host computer 1h30'
        Speaker: Bruno VALINOTI (Instituto Nacional de Tecnologia Industrial, Argentina)
      • 15:30 Coffee break 30'
      • 16:00 FPGAs computing just right thanks to application-specific arithmetic 1h30'
        Speaker: Florent DE DINECHIN (Lyon, France)
        Material: Slides
      • 17:30 Lab activities with tutors 1h0'
  • Wednesday, 22 May 2019
    • 09:00 - 18:30
      • 09:00 High-Performance Computing at the ICTP 1h30'
        Speaker: Ivan GIROTTO (ICTP)
        Material: Slides
      • 10:30 Coffee break 30'
      • 11:00 The FloPoCo arithmetic core generator 1h30'
        Speaker: Florent DE DINECHIN (Lyon, France)
        Material: Slides
      • 12:30 Lunch break 1h30'
      • 14:00 Feature Extraction from Waveforms and Data Compression 1h30'
        Speaker: Grzegorz PASTUSZAK (Warsaw University of Technology, Warsaw, Poland)
        Material: Slides
      • 15:30 Coffee break 30'
      • 16:00 Introduction to Parallel Computing using FPGAs 1h0'
        Speaker: Abelardo JARA-BERROCAL (Megh Computing, USA)
      • 17:00 Writing OpenCL programs for FPGAs 1h30'
        Speaker: Abelardo JARA-BERROCAL (Megh Computing, USA)
  • Thursday, 23 May 2019
    • 09:00 - 18:30
      • 09:00 Optimizing OpenCL programs for FPGAs 1h30'
        Speaker: Abelardo JARA-BERROCAL (Megh Computing, USA)
      • 10:30 Coffee break 30'
      • 11:00 Software Application Stack for FPGAs (OPAE and SIRA) 1h30'
        Speaker: Abelardo JARA-BERROCAL (Megh Computing, USA)
      • 12:30 Lunch break 1h30'
      • 14:00 Developing and Debugging RTL-based Accelerator Units on FPGAs 1h30'
        Speaker: Abelardo JARA-BERROCAL (Megh Computing, USA)
      • 15:30 Coffee break 30'
      • 16:00 Lab Tutorial: FloPoCo for Scientific Computing 1h0'
        Speaker: Luis Garcia ORDONEZ (ICTP / Guatemala)
      • 17:00 Lab activities with tutors 1h30'
    • 19:30 - 20:30
      • 19:30 Farewell Reception 1h0' ( Adriatico GuestHouse - Cafeteria )
        All participants are cordially invited to the Farewell Reception.
  • Friday, 24 May 2019
    • 09:00 - 17:00
      • 09:00 Lab Tutorial: Advanced project based on SoC for Scientific Computing 1h30'
        Speaker: Kasun S. MANNATUNGA (University of Moratuwa, Sri Lanka)
      • 10:30 Coffee break 30'
      • 11:00 Lab activities with tutors 1h30'
      • 12:30 Lunch break 1h30'
      • 14:00 Lab activities with tutors 1h30'
      • 15:30 Coffee break 30'
      • 16:00 Concluding Remarks and Distribution of Certificates 1h0'
        Speaker: Maria Liz CRESPO (ICTP), Andres CICUTTIN (ICTP)