Go to day
  • Monday, 26 October 2009
    • 08:30 - 11:30 Registration & Administrative Formalities
      Location: Adriatico Guest House - Kastler Lecture Hall Area (Lower Level 1)
      • 08:30 Registration & Administrative Formalities 3h0'
    • 11:30 - 11:45 Opening Address
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:30 Opening Address 15'
        Speaker: C.Tuniz (Assistant Director, ICTP)
    • 11:45 - 12:00 Course Introduction
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:45 Course Introduction 15'
        Speaker: N. Abdallah (Actel Corp., CA, USA)
    • 12:00 - 12:15 Course Overview
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 Course Overview 15'
        Speaker: A. Cicuttin (ICTP)
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Introduction to FPGA Synthesis. Introduction to VHDL
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 Introduction to FPGA Synthesis. Introduction to VHDL 1h0'
        Speaker: N. Abdallah
        Material: lecture notes
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 Introduction to Actel Prodcuts. Libero IDE Overview and Design Flow
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Introduction to Actel Prodcuts. Libero IDE Overview and Design Flow 1h0'
        Speaker: N. Abdallah
    • 17:00 - 18:00 Introduction to Digital Design
      Location: Adriatico Guest House Kastler Lecture Hall
      • 17:00 Introduction to Digital Design 1h0'
        Speaker: P. Bazargan-Sabet (University Pierre & Marie Curie, LIP6, Paris, France)
        Material: lecture notes
  • Tuesday, 27 October 2009
    • 09:30 - 10:30 Digital Design I (Combinatorial elements)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Digital Design I (Combinatorial elements) 1h0'
        Speaker: P. Bazargan-Sabet
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Digital Design II (Sequential elements, Mealy and Moore FSM)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Digital Design II (Sequential elements, Mealy and Moore FSM) 1h0'
        Speaker: P. Bazargan-Sabet
    • 12:00 - 13:00 Sinthesis I - Introduction to VHDL
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 Sinthesis I - Introduction to VHDL 1h0'
        Speaker: N. Abdallah
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Sinthesis II - Introduction to VHDL
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 Sinthesis II - Introduction to VHDL 1h0'
        Speaker: N. Abdallah
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 (LiberoTM IDE) Design Entry
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 (LiberoTM IDE) Design Entry 1h0'
        Speaker: N. Abdallah
    • 17:00 - 18:00 (LiberoTM IDE) Functional Simulation. Synthesis
      Location: Adriatico Guest House Kastler Lecture Hall
      • 17:00 (LiberoTM IDE) Functional Simulation. Synthesis 1h0'
        Speaker: N. Abdallah
  • Wednesday, 28 October 2009
    • 09:30 - 10:30 Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc) 1h0'
        Speaker: P. Bazargan-Sabet
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Digital arithmetic I (number representations)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Digital arithmetic I (number representations) 1h0'
        Speaker: P. Bazargan-Sabet
    • 12:00 - 13:00 Synthesis III - Advanced VHDL
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 Synthesis III - Advanced VHDL 1h0'
        Speaker: N. Abdallah
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 (LiberoTM IDE) Place & Route
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 (LiberoTM IDE) Place & Route 1h0'
        Speaker: N. Abdallah
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 Design Verification and Timing Concepts
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Design Verification and Timing Concepts 1h0'
        Speaker: N. Abdallah
    • 17:00 - 18:00 (LiberoTM IDE) Timing Constraints and Analysis
      Location: Adriatico Guest House Kastler Lecture Hall
      • 17:00 (LiberoTM IDE) Timing Constraints and Analysis 1h0'
        Speaker: N. Abdallah
    • 18:00 - 19:30 Reception
      Location: Adriatico Guest House Kastler Lecture Hall
      • 18:00 Reception 1h30'
  • Thursday, 29 October 2009
    • 09:30 - 10:30 Digital arithmetic II (basic arithmetic operations)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Digital arithmetic II (basic arithmetic operations) 1h0'
        Speaker: P. Bazargan-Sabet
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Programmable logic & FPGA architectures
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Programmable logic & FPGA architectures 1h0'
        Speaker: N. Abdallah
    • 12:00 - 13:00 (LiberoTM IDE) Post-Layout Simulation. Programming
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 (LiberoTM IDE) Post-Layout Simulation. Programming 1h0'
        Speaker: N. Abdallah
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session. VHDL Simulation Environment. A design example
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. VHDL Simulation Environment. A design example 1h0'
        Speaker: M.L. Crespo
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits.
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. 2h0'
        Speaker: M.L. Crespo
  • Friday, 30 October 2009
    • 09:30 - 10:30 Actel Fusion FPGA Architecture
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Actel Fusion FPGA Architecture 1h0'
        Speaker: N. Abdallah
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Actel Fusion FPGA Architecture (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Actel Fusion FPGA Architecture (cont.) 1h0'
        Speaker: N. Abdallah
    • 12:00 - 13:00 Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
      Location: Adriatico Guest House Informatics Lab.
      • 12:00 Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits 1h0'
        Speaker: M. L. Crespo
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits.
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits. 1h0'
        Speaker: M.L. Crespo
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits (Cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits (Cont.) 2h0'
        Speaker: M.L. Crespo
  • Monday, 2 November 2009
    • 09:30 - 10:30 The Actel Fusion Embedded Development Kit
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 The Actel Fusion Embedded Development Kit 1h0'
        Speaker: N. Abdallah
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 The Actel Fusion Embedded Development Kit (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 The Actel Fusion Embedded Development Kit (cont.) 1h0'
        Speaker: N. Abdallah
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.) 1h0'
        Speaker: M.L. Crespo
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.) 2h0'
        Speaker: M.L. Crespo
  • Tuesday, 3 November 2009
    • 09:30 - 10:30 Laboratory Session. Synthesis and Post-Synthesis Simulation
      Location: Adriatico Guest House Informatics Lab.
      • 09:30 Laboratory Session. Synthesis and Post-Synthesis Simulation 1h0'
        Speaker: M.L. Crespo
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 11:00 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.) 2h0'
        Speaker: M.L. Crespo
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.) 1h0'
        Speaker: M.L. Crespo
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.) 2h0'
        Speaker: M.L. Crespo
  • Wednesday, 4 November 2009
    • 09:30 - 10:30 Presentation of FPGA Projects by Participants and Discussion
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Presentation of FPGA Projects by Participants and Discussion 1h0'
        Material: Presentations
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Presentation of FPGA Projects by Participants and Discussion (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Presentation of FPGA Projects by Participants and Discussion (cont.) 2h0'
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Presentation of FPGA Projects by Participants and Discussion
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 Presentation of FPGA Projects by Participants and Discussion 1h0'
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Presentation of FPGA Projects by Participants and Discussion
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Presentation of FPGA Projects by Participants and Discussion 2h0'
  • Thursday, 5 November 2009
    • 09:30 - 10:30 Selected Topics on Logic Synthesis and FPGA Debugging
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Selected Topics on Logic Synthesis and FPGA Debugging 1h0'
        Speaker: A. Cicuttin
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Selected Topics on Logic Synthesis and FPGA Debugging (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Selected Topics on Logic Synthesis and FPGA Debugging (cont.) 1h0'
        Speaker: A. Cicuttin
    • 12:00 - 13:00 Laboratory Session. Hardware Description of the FPGA Development Platform.
      Location: Adriatico Guest House Informatics Lab.
      • 12:00 Laboratory Session. Hardware Description of the FPGA Development Platform. 1h0'
        Speaker: C. Sosa Paez (UNSL, San Luis, Argentina)
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session. Hardware Description of the FPGA Development Platform (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. Hardware Description of the FPGA Development Platform (cont.) 1h0'
        Speaker: C. Sosa Paez
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. FPGA Implementation Example.
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. FPGA Implementation Example. 2h0'
        Speaker: C. Sisterna (UNSJ, San Juan, Argentina)
  • Friday, 6 November 2009
    • 09:30 - 10:30 Reconfigurable Virtual Instrumentation (RVI) based on FPGA
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Reconfigurable Virtual Instrumentation (RVI) based on FPGA 1h0'
        Speaker: A. Cicuttin
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.) 1h0'
        Speaker: A. Cicuttin
    • 12:00 - 13:00 System-on-Chip Concepts.
      Location: Adriatico Guest House Informatics Lab.
      • 12:00 System-on-Chip Concepts. 1h0'
        Speaker: N. Abdallah
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 System-on-Chip Concepts (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 System-on-Chip Concepts (cont.) 1h0'
        Speaker: N. Abdallah
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. Implementation in the FPGA Development Platform
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. Implementation in the FPGA Development Platform 2h0'
        Speaker: M.L. Crespo
  • Monday, 9 November 2009
    • 09:30 - 10:30 Introduction to Digital Signal Processing
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Introduction to Digital Signal Processing 1h0'
        Speaker: M. Nolich (University of Trieste, Italy)
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Discrete Time Signals and Systems
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Discrete Time Signals and Systems 2h0'
        Speaker: M. Nolich
    • 13:00 - 14:30 Lunch Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 The µLab Virtual Pannel
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 The µLab Virtual Pannel 1h0'
        Speaker: M.A. Risco Castillo (Technological University of Peru, Lima, Peru)
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 The µLab Virtual Pannel. A design example.
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 The µLab Virtual Pannel. A design example. 2h0'
        Speaker: M. Risco Castillo
  • Tuesday, 10 November 2009
    • 09:30 - 10:30 Advanced FPGA Applications
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Advanced FPGA Applications 1h0'
        Speaker: A. Kluge (CERN, Geneva, Switzerland)
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 A case study in HEP experiments (I)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 A case study in HEP experiments (I) 2h0'
        Speaker: A. Kluge
    • 13:00 - 14:00 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h0'
    • 14:30 - 15:30 The Z-Transform
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 The Z-Transform 1h0'
        Speaker: M. Nolich
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 Sampling of Continuous-Time Signals
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Sampling of Continuous-Time Signals 1h0'
        Speaker: M. Nolich
    • 17:00 - 18:00 Laboratory Session. Digital Arithmetic.
      Location: Adriatico Guest House Informatics Lab.
      • 17:00 Laboratory Session. Digital Arithmetic. 1h0'
        Speaker: M. L. Crespo
  • Wednesday, 11 November 2009
    • 09:30 - 10:30 A case study in HEP experiments (II)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 A case study in HEP experiments (II) 1h0'
        Speaker: A. Kluge
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 A case study in HEP experiments (III)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 A case study in HEP experiments (III) 1h0'
        Speaker: A. Kluge
    • 12:00 - 13:00 The Discrete Fourier Transform
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 The Discrete Fourier Transform 1h0'
        Speaker: M. Nolich
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Transform Analysis of LTI Systems
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 Transform Analysis of LTI Systems 1h0'
        Speaker: M. Nolich
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 Digital Filters Design
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Digital Filters Design 1h0'
        Speaker: M. Nolich
    • 17:00 - 18:00 Laboratory Session. Digital Arithmetic (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 17:00 Laboratory Session. Digital Arithmetic (cont.) 1h0'
        Speaker: M. L. Crespo
  • Thursday, 12 November 2009
    • 09:30 - 10:30 FPGA-based Custom Board Design for Instrumentation
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 FPGA-based Custom Board Design for Instrumentation 1h0'
        Speaker: K.M. Khare (RRCAT, Indore, India)
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Advanced VHDL Subjects
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Advanced VHDL Subjects 2h0'
        Speaker: C. Sisterna
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session: Waveform generation
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session: Waveform generation 1h0'
        Speaker: M.L. Crespo
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session: Waveform generation (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session: Waveform generation (cont.) 2h0'
        Speaker: M.L. Crespo
  • Friday, 13 November 2009
    • 09:30 - 10:30 Advanced FPGA Subjects
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Advanced FPGA Subjects 1h0'
        Speaker: C. Sisterna
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Advanced FPGA Subjects (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Advanced FPGA Subjects (cont.) 1h0'
        Speaker: C. Sisterna
    • 12:00 - 13:00 Digital Filters Design (cont.)
      Location: Adriatico Guest House Kastler Lecture Hall
      • 12:00 Digital Filters Design (cont.) 1h0'
        Speaker: M. Nolich
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Laboratory Session: ICTP RVI Platform Description
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session: ICTP RVI Platform Description 1h0'
        Speaker: K.M. Khare
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 17:00 Laboratory Session: DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope (cont.)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session: DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope (cont.) 1h0'
        Speaker: M. Risco Castillo, J. Lopez Botero
    • 17:00 - 18:00 Laboratory Session: ICTP RVI Platform. A Design Example.
      Location: Adriatico Guest House Informatics Lab.
      • 17:00 Laboratory Session: ICTP RVI Platform. A Design Example. 1h0'
        Speaker: K.M. Khare
  • Monday, 16 November 2009
    • 09:30 - 10:30 Introduction to two-dimensional digital signal processing
      Location: Adriatico Guest House Kastler Lecture Hall
      • 09:30 Introduction to two-dimensional digital signal processing 1h0'
        Speaker: F. Mammano (University of Padova, Italy)
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Two-dimensional digital signal processing
      Location: Adriatico Guest House Kastler Lecture Hall
      • 11:00 Two-dimensional digital signal processing 2h0'
        Speaker: F. Mammano
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Three-dimensional deconvolution in FPGA
      Location: Adriatico Guest House Kastler Lecture Hall
      • 14:30 Three-dimensional deconvolution in FPGA 1h0'
        Speaker: F. Mammano
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Kastler Lecture Hall
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session: Digital Signal Processing with FPGA. A design example.
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session: Digital Signal Processing with FPGA. A design example. 2h0'
        Speaker: C. Sosa Paez
  • Tuesday, 17 November 2009
    • 09:30 - 10:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
      Location: Adriatico Guest House Informatics Lab.
      • 09:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA. 1h0'
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 11:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 2h0'
    • 13:00 - 14:30 Lunch break
      Location: Adriatico Guest House Informatics Lab.
      • 13:00 Lunch break 1h30'
    • 14:30 - 15:30 Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB)
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB) 1h0'
    • 15:30 - 16:00 Coffee Break at the MLAB
      Location: Adriatico Guest House Informatics Lab.
      • 15:30 Coffee Break at the MLAB 30'
    • 16:00 - 18:00 Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB)
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB) 2h0'
  • Wednesday, 18 November 2009
    • 09:30 - 10:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 09:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 1h0'
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 11:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 2h0'
    • 13:00 - 14:00 Lunch break
      Location: Adriatico Guest House Informatics Lab.
      • 13:00 Lunch break 1h0'
    • 14:30 - 15:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 30'
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Darwin & Modern Science
      More details on:
      http://pio.ictp.it/words/news/2009/darwin-and-modern-science
      Location: Leonardo da Vinci Building Main Lecture Hall
      • 16:00 Darwin & Modern Science 2h0'
  • Thursday, 19 November 2009
    • 09:30 - 10:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 09:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 1h0'
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 11:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 2h0'
    • 13:00 - 14:00 Lunch break
      Location: Adriatico Guest House Informatics Lab.
      • 13:00 Lunch break 1h0'
    • 14:30 - 15:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 1h0'
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Distribution of Diplomas of Attendance
      Location: Adriatico Guest House Kastler Lecture Hall
      • 16:00 Distribution of Diplomas of Attendance 2h0'
    • 18:30 - 20:00 Get-Together
      Location: Adriatico Guest House Informatics Lab. - Room alternative: Adriatico Guest House Cafeteria
      • 18:30 Get-Together 1h30'
  • Friday, 20 November 2009
    • 09:30 - 10:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 09:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 1h0'
    • 10:30 - 11:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 10:30 Coffee Break 30'
    • 11:00 - 13:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 11:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 2h0'
    • 13:00 - 14:00 Lunch break
      Location: Adriatico Guest House Informatics Lab.
      • 13:00 Lunch break 1h0'
    • 14:30 - 15:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 14:30 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 1h0'
    • 15:30 - 16:00 Coffee Break
      Location: Adriatico Guest House Informatics Lab.
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 16:00 Laboratory Session. RVI Projects. Digital Signal Processing with FPGA 2h0'