Description
Venue: CAECE University  
Go to day
  • Monday, 15 March 2010
    • 09:00 - 11:30 REGISTRATION AND ADMINISTRATIVE FORMALITIES
      Location: - Room alternative: LOBBY, UCAECE UNIVERSITY MAIN ENTRANCE
      • 09:00 REGISTRATION AND ADMINISTRATIVE FORMALITIES 2h30'
    • 11:30 - 13:00 OPENING CEREMONY
      Location: - Room alternative: AULA MAGNA CAECE UNIVERSITY
      • 11:30 OPENING CEREMONY 1h30'
    • 13:00 - 14:00 Lunch
      • 13:00 Lunch 1h0'
    • 14:00 - 15:00 FPGA Design and VHDL. Overview.
      • 14:00 FPGA Design and VHDL. Overview. 1h0'
        Speaker: Nizar Abdallah
    • 15:00 - 15:30 Coffee break
      • 15:00 Coffee break 30'
    • 15:30 - 16:30 FPGA Architectures & VHDL. Introduction to FPGAs & FPGA Design Flow.
      • 15:30 FPGA Architectures & VHDL. Introduction to FPGAs & FPGA Design Flow. 1h0'
        Speaker: Nizar Abdallah
    • 16:30 - 17:30 Introduction to Digital Design.
      • 16:30 Introduction to Digital Design. 1h0'
        Speaker: Pirouz Bazargan-Sabet (LIP6, University Pierre et Matie Curie, Paris, France)
        Material: lecture notes
    • 17:30 - 18:30 Digital Design I (combinatorial elements).
      • 17:30 Digital Design I (combinatorial elements). 1h0'
        Speaker: Pirouz Bazargan-Sabet
  • Tuesday, 16 March 2010
    • 09:00 - 10:00 Digital Design II (sequential elements, Mealy and Moore FSM).
      • 09:00 Digital Design II (sequential elements, Mealy and Moore FSM). 1h0'
        Speaker: Pirouz Bazargan-Sabet
        Material: lecture notes
    • 10:00 - 11:00 FPGA Architectures & VHDL. Introduction to Synthesis.
      • 10:00 FPGA Architectures & VHDL. Introduction to Synthesis. 1h0'
        Speaker: Nizar Abdallah
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Synthesis II - Introduction to VHDL.
      • 11:30 Synthesis II - Introduction to VHDL. 1h0'
        Speaker: Nizar Abdallah
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 (LiberoTM IDE) Design Entry.
      • 14:00 (LiberoTM IDE) Design Entry. 1h0'
        Speaker: Nizar Abdallah
    • 15:00 - 16:00 Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc).
      • 15:00 Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc). 1h0'
        Speaker: Pirouz Bazargan-Sabet
        Material: lecture notes
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 17:30 (LiberoTM IDE) Functional Simulation. Synthesis.
      • 16:30 (LiberoTM IDE) Functional Simulation. Synthesis. 1h0'
        Speaker: Nizar Abdallah
    • 17:30 - 18:30 Synthesis III - Advanced VHDL.
      • 17:30 Synthesis III - Advanced VHDL. 1h0'
        Speaker: Nizar Abdallah
  • Wednesday, 17 March 2010
    • 09:00 - 10:00 Digital arithmetic I (number representations).
      • 09:00 Digital arithmetic I (number representations). 1h0'
        Speaker: Pirouz Bazargan-Sabet
        Material: lecture notes
    • 10:00 - 11:00 (LiberoTM IDE) Place & Route.
      • 10:00 (LiberoTM IDE) Place & Route. 1h0'
        Speaker: Nizar Abdallah
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Design Verification and Timing Concepts.
      • 11:30 Design Verification and Timing Concepts. 1h0'
        Speaker: Nizar Abdallah
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 (LiberoTM IDE) Timing Constraints and Analysis
      • 14:00 (LiberoTM IDE) Timing Constraints and Analysis 1h0'
        Speaker: Nizar Abdallah
    • 15:00 - 16:00 Digital arithmetic II (basic arithmetic operations).
      • 15:00 Digital arithmetic II (basic arithmetic operations). 1h0'
        Speaker: Pirouz Bazargan-Sabet
        Material: lecture notes
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 17:30 Programmable logic & FPGA architectures
      • 16:30 Programmable logic & FPGA architectures 1h0'
        Speaker: Nizar Abdallah
    • 17:30 - 18:30 (LiberoTM IDE) Post-Layout Simulation. FPGA Programming.
      • 17:30 (LiberoTM IDE) Post-Layout Simulation. FPGA Programming. 1h0'
        Speaker: Nizar Abdallah
  • Thursday, 18 March 2010
    • 09:00 - 10:00 Actel Fusion FPGA architecture.
      • 09:00 Actel Fusion FPGA architecture. 1h0'
        Speaker: Nizar Abdallah
    • 10:00 - 11:00 Actel Fusion FPGA architecture (cont.)
      • 10:00 Actel Fusion FPGA architecture (cont.) 1h0'
        Speaker: Nizar Abdallah
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 The Actel Fusion Embedded Development Kit
      • 11:30 The Actel Fusion Embedded Development Kit 1h0'
        Speaker: Nizar Abdallah
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 The Actel Fusion Embedded Development Kit (cont.)
      • 14:00 The Actel Fusion Embedded Development Kit (cont.) 1h0'
        Speaker: Nizar Abdallah
    • 15:00 - 16:00 Laboratory Overview. VHDL Simulation Environment. A design example.
      • 15:00 Laboratory Overview. VHDL Simulation Environment. A design example. 1h0'
        Speaker: Maria Liz Crespo (ICTP Multidisciplinary Laboratory, Trieste, Italy)
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits.
      • 16:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits. 2h0'
  • Friday, 19 March 2010
    • 09:00 - 10:00 System-on-Chip concepts
      • 09:00 System-on-Chip concepts 1h0'
        Speaker: Nizar Abdallah
    • 10:00 - 11:00 System-on-Chip concepts (cont.)
      • 10:00 System-on-Chip concepts (cont.) 1h0'
        Speaker: Nizar Abdallah
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
      • 11:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.) 1h0'
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
      • 14:00 Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.) 1h0'
    • 15:00 - 16:00 Basic Add and Subtract Operations in VHDL. Case examples.
      • 15:00 Basic Add and Subtract Operations in VHDL. Case examples. 1h0'
        Speaker: Cristian Sisterna (University of San Juan, Argentina)
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits
      • 16:30 Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits 2h0'
  • Monday, 22 March 2010
    • 09:00 - 10:00 Microelectronics at CERN
    • 10:00 - 11:00 Introduction to CMOS Technology and VLSI Design.
      • 10:00 Introduction to CMOS Technology and VLSI Design. 1h0'
        Speaker: Paulo Rodrigues S. Moreira
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 CMOS Technology I
      • 11:30 CMOS Technology I 1h0'
        Speaker: Paulo Rodrigues S. Moreira
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 16:00 Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits (cont.)
      • 14:00 Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits (cont.) 2h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: Finite State Machine. VHDL Description and Simulation.
      • 16:30 Laboratory Exercises: Finite State Machine. VHDL Description and Simulation. 2h0'
  • Tuesday, 23 March 2010
    • 09:00 - 10:00 Introduction to Fourier Theory.
      • 09:00 Introduction to Fourier Theory. 1h0'
        Speaker: Marcelo Magnasco (Rockfeller University, NY, USA)
    • 10:30 - 11:30 Fourier Theory I.
      • 10:30 Fourier Theory I. 1h0'
        Speaker: Marcelo Magnasco
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 CMOS Technology II.
      • 11:30 CMOS Technology II. 1h0'
        Speaker: Paulo Rodrigues S. Moreira
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 VLSI Design.
      • 14:00 VLSI Design. 1h0'
        Speaker: Paulo Rodrigues S. Moreira
    • 15:00 - 16:00 Laboratory Exercises: Finite State Machine. VHDL Description and Simulation (cont.)
      • 15:00 Laboratory Exercises: Finite State Machine. VHDL Description and Simulation (cont.) 1h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation.
      • 16:30 Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation. 2h0'
  • Wednesday, 24 March 2010
    • 09:00 - 10:00 Fourier Theory II.
      • 09:00 Fourier Theory II. 1h0'
        Speaker: Marcelo Magnasco
    • 10:00 - 11:00 Introduction to Digital Signal Processing.
      • 10:00 Introduction to Digital Signal Processing. 1h0'
        Speaker: Marcelo Magnasco
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Advanced FPGA Applications.
      • 11:30 Advanced FPGA Applications. 1h0'
        Speaker: Alexander Kluge (CERN, Geneva, Switzerland)
        Material: lecture notes
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 A case study in HEP experiments I.
      • 14:00 A case study in HEP experiments I. 1h0'
        Speaker: Alexander Kluge
        Material: lecture notes
    • 15:00 - 16:00 Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation (cont.)
      • 15:00 Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation (cont.) 1h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 17:30 Hardware Description of the FPGA Development Platform.
      • 16:30 Hardware Description of the FPGA Development Platform. 1h0'
        Speaker: Carlos Sosa Paez (University of San Luis, Argentina)
    • 17:30 - 18:30 FPGA Implementation Example.
      • 17:30 FPGA Implementation Example. 1h0'
        Speaker: Cristian Sisterna
  • Thursday, 25 March 2010
    • 09:00 - 10:00 Digital Signal Processing I
      • 09:00 Digital Signal Processing I 1h0'
        Speaker: Marcelo Magnasco
    • 10:00 - 11:00 Digital Signal Processing II
      • 10:00 Digital Signal Processing II 1h0'
        Speaker: Marcelo Magnasco
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 A case study in HEP experiments II
      • 11:30 A case study in HEP experiments II 1h0'
        Speaker: Alexander Kluge
        Material: lecture notes
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 A case study in HEP experiments III
      • 14:00 A case study in HEP experiments III 1h0'
        Speaker: Alexander Kluge
    • 15:00 - 16:00 Laboratory Exercises: Implementation in the FPGA Development Platform.
      • 15:00 Laboratory Exercises: Implementation in the FPGA Development Platform. 1h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: Implementation in the FPGA Development Platform (contd.)
      • 16:30 Laboratory Exercises: Implementation in the FPGA Development Platform (contd.) 2h0'
  • Friday, 26 March 2010
    • 09:00 - 10:00 Selected topics on Logic Synthesis and FPGA Debugging.
      • 09:00 Selected topics on Logic Synthesis and FPGA Debugging. 1h0'
        Speaker: Andres Cicuttin
    • 10:00 - 11:00 Selected topics on Logic Synthesis and FPGA Debugging (cont.)
      • 10:00 Selected topics on Logic Synthesis and FPGA Debugging (cont.) 1h0'
        Speaker: Andres Cicuttin
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Reconfigurable Virtual Instrumentation (RVI) based on FPGA.
      • 11:30 Reconfigurable Virtual Instrumentation (RVI) based on FPGA. 1h0'
        Speaker: Andres Cicuttin
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
      • 14:00 Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.) 1h0'
        Speaker: Andres Cicuttin
    • 15:00 - 16:00 The µLab Virtual Panel. A design example.
      • 15:00 The µLab Virtual Panel. A design example. 1h0'
        Speaker: Miguel Risco Castillo
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 17:30 The µLab Virtual Panel. A design example. (contd).
      • 16:30 The µLab Virtual Panel. A design example. (contd). 1h0'
    • 17:30 - 18:30 Laboratory Exercises: Implementation in the FPGA Development Platform (cont.)
      • 17:30 Laboratory Exercises: Implementation in the FPGA Development Platform (cont.) 1h0'
  • Monday, 29 March 2010
    • 09:00 - 10:00 Radiation Effects in Semiconductor Devices.
      • 09:00 Radiation Effects in Semiconductor Devices. 1h0'
        Speaker: Felix Palumbo (CONICET - CNEA, Buenos Aires)
    • 10:00 - 11:00 Radiation Effects in Semiconductor Devices.
      • 10:00 Radiation Effects in Semiconductor Devices. 1h0'
        Speaker: Felix Palumbo
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Advanced Data Acquisition and Processing System for a HEP Experiment at CERN
      • 11:30 Advanced Data Acquisition and Processing System for a HEP Experiment at CERN 1h0'
        Speaker: Maria Liz Crespo
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 16:00 Laboratory Exercises: Digital Arithmetic.
      • 14:00 Laboratory Exercises: Digital Arithmetic. 2h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: Waveform generation
      • 16:30 Laboratory Exercises: Waveform generation 2h0'
  • Tuesday, 30 March 2010
    • 09:00 - 10:00 ICTP RVI Platform Description.
      • 09:00 ICTP RVI Platform Description. 1h0'
        Speaker: Andres Airabella (University of San Luis, Argentina)
    • 10:00 - 11:00 DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope
      • 10:00 DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope 1h0'
        Speaker: Miguel Risco Castillo
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Digital Signal Processing with FPGA. A Design Example: Differentiator.
      • 11:30 Digital Signal Processing with FPGA. A Design Example: Differentiator. 1h0'
        Speaker: Carlos Sosa Paez
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 Digital Signal Processing with FPGA. A Design Example: Differentiator (cont.)
      • 14:00 Digital Signal Processing with FPGA. A Design Example: Differentiator (cont.) 1h0'
        Speaker: Carlos Sosa Paez
    • 15:00 - 16:00 Laboratory Exercises: Digital Signal Processing with FPGA.
      • 15:00 Laboratory Exercises: Digital Signal Processing with FPGA. 1h0'
    • 16:00 - 16:30 Coffee break
      • 16:00 Coffee break 30'
    • 16:30 - 18:30 Laboratory Exercises: Digital Signal Processing with FPGA. (contd.)
      • 16:30 Laboratory Exercises: Digital Signal Processing with FPGA. (contd.) 2h0'
  • Wednesday, 31 March 2010
    • 09:00 - 10:00 Laboratory Exercises: Digital Signal Processing with FPGA.
      • 09:00 Laboratory Exercises: Digital Signal Processing with FPGA. 1h0'
    • 10:00 - 11:00 Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter).
      • 10:00 Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter). 1h0'
        Speaker: Andres Airabella
    • 11:00 - 11:30 Coffee break
      • 11:00 Coffee break 30'
    • 11:30 - 12:30 Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter) (contd).
      • 11:30 Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter) (contd). 1h0'
    • 12:30 - 14:00 Lunch
      • 12:30 Lunch 1h30'
    • 14:00 - 15:00 General Discussions and Concluding Remarks
      • 14:00 General Discussions and Concluding Remarks 1h0'
    • 15:00 - 15:30 Coffee break
      • 15:00 Coffee break 30'
    • 15:30 - 16:30 Distribution of Diplomas of Attendance
      • 15:30 Distribution of Diplomas of Attendance 1h0'
    • 16:30 - 18:30 Get-Together Drink
      • 16:30 Get-Together Drink 2h0'