Description
PURPOSE OF THE SCHOOL

The school is intended as a hands-on training activity that will provide an opportunity for physicists, engineers and computer scientists to access new technologies and gain the necessary skills for designing and developing complete high-performance systems for scientific applications at low cost.
The practical sessions of the school will be based on FPGA platforms, IDE software tools and VHDL hardware description language. 
The school will also introduce modern hybrid system-on-chip devices that combine the software programmability of general purpose processors with the hardware reconfigurability of FPGA.
It is expected to enhance the capabilities of researchers, teachers and advanced students from Asia who are seeking to exploit modern technologies for challenging scientific and academic purposes. 


PARTICIPATION

Scientists and students from Asian countries that are members of the United Nations, UNESCO or IAEA may apply to attend.  As the School will be conducted in English participants should have an adequate working knowledge of it. 
Go to day
  • Monday, 7 December 2015
    • 08:30 - 14:00 INAUGURAL CEREMONY
      • 08:30 Registration 1h30' ( Late Haji Mehmood Senate Hall, Main Admin Building, MUET, Jamshoro )
      • 10:00 Recitation from Holy Quran 10'
      • 10:10 Welcome Speech 20' ( MUET, Jamshoro )
        Speaker: Prof. Dr. Muhammad Aslam Uqaili (Vice Chancellor)
      • 10:30 MUET Goes Global 15'
        Speaker: Prof. Dr. Bhawani Shankar Chowdhry (Dean Faculty of Electrical, Electronics & Computer Engineering, MUET, Jamshoro)
      • 10:45 Multidisciplinary Laboratory at ICTP 15'
        Speaker: Dr. Maria Liz Crespo (Research Officer and Workshop Co-Director, ICTP Multidisciplinary Laboratory, ICTP, Italy)
      • 11:00 Workshop Overview 15' ( Department of Electronic Engineering, MUET, Jamshoro )
        Speaker: Dr. Tayab Din Memon (Associate Professor)
      • 11:15 Inaugural Speech 30'
        Speaker: Chief Guest: Dr. Manzoor Soomro
      • 11:45 Coffee Break and Lunch 2h15'
    • 14:00 - 20:30 AFTERNOON SESSION
      • 14:00 FPGA & VHDL Fundamentals 2h0'
        Speaker: Sisterna Cristian Alejandro (University of San Juan, Argentina)
      • 16:00 Coffee Break 30'
      • 16:30 Digital and Arithmetic Design 2h0'
        Speaker: Imtiaz Hussain Kalwar (Mehran University of Engineering & Technology, Pakistan)
      • 18:30 Welcome Dinner 2h0'
  • Tuesday, 8 December 2015
    • 08:30 - 20:00
      • 08:30 VHDL Design 2h0'
        Speaker: Sisterna Cristian Alejandro
      • 10:30 Coffee Break 30'
      • 11:00 Inside the FPGA 1h0'
        Speaker: Sandro Bonacini (Centre for European Research for Nuclear Research CERN, Switzerland)
      • 12:00 Lunch 1h30'
      • 13:30 Inside the FPGA 2h0'
        Speaker: Sandro Bonacini
      • 15:30 Coffee Break 30'
      • 16:00 VHDL Design 2h0'
        Speaker: Sisterna Cristian Alejandro
      • 18:00 Dinner 2h0'
  • Wednesday, 9 December 2015
    • 08:30 - 20:00
      • 08:30 CMOS Technology and VLSI Design 2h0'
        Speaker: Sandro Bonacini
      • 10:30 Coffee Break 30'
      • 11:00 Evolution of Reconfigurable Devices 1h0'
        Speaker: Yousaf Zafar (Institute ICCC Atomic Energy Commission,Pakistan)
      • 12:00 Lunch 1h30'
      • 13:30 Fundamentals on Digital Signal Processing 2h0'
        Speaker: Wanod Kumar (Mehran University of Engineering and Technology, Jamshoro PAKISTAN)
      • 15:30 Coffee Break 30'
      • 16:00 VHDL Design 2h0'
        Speaker: Sisterna Cristian Alejandro
      • 18:00 Dinner 2h0'
  • Thursday, 10 December 2015
    • 08:30 - 20:00
      • 08:30 Evolution of Reconfigurable Devices 2h0'
        Speaker: Yousaf Zafar
      • 10:30 Coffee Break 30'
      • 11:00 Fundamentals on Digital Signal Processing 1h0'
        Speaker: Wanod Kumar
      • 12:00 Lunch 1h30'
      • 13:30 Overview of Laboratory Sessions 1h0'
        Speaker: Maria Liz Crespo (ICTP Multidisciplinary Laboratory, Italy)
      • 14:30 ISE, Isim, Impact - Xilinx EDA Tools (Lab. Tutorial) 1h0'
        Speaker: Sisterna Cristian Alejandro
      • 15:30 Coffee Break 30'
      • 16:00 Laboratory Session 2h0'
        Speaker: Instructors
      • 18:00 Dinner 2h0'
  • Friday, 11 December 2015
    • 08:30 - 20:00
      • 08:30 Laboratory Session 2h0'
        Speaker: Instructors
      • 10:30 Coffee Break 30'
      • 11:00 Laboratory Session 1h0'
        Speaker: Instructors
      • 12:00 Lunch 1h30'
      • 13:30 Hardware Description of FPGA Development Platform - Design Example (Lab. Tutorial) 2h0'
        Speaker: Mannatunga Kasun Sameera (University of Moratuwa, Sri Lanka)
      • 15:30 Coffee Break 30'
      • 16:00 Laboratory Session 2h0'
        Speaker: Instructors
      • 18:00 Dinner 2h0'
  • Monday, 14 December 2015
    • 08:30 - 20:00
      • 08:30 Heterogeneous FPGA architectures 2h0'
        Speaker: Hussain Parvez (Karachi Institute of Economics & Technology (KIET), Pakistan)
      • 10:30 Coffee Break 30'
      • 11:00 Developing your own Mesh-based FPGA Architecture 1h0'
        Speaker: Hussain Parvez
      • 12:00 Lunch 1h30'
      • 13:30 Laboratory Session 2h0'
        Speaker: Instructors
      • 15:30 Coffee Break 30'
      • 16:00 Synthesis and Implementation of a Sequential Digital System in FPGA (Lab. Tutorial) 2h0'
        Speaker: Hafeezullah Qazi (Marine Systems Pvt Limited MSL, Pakistan)
      • 18:00 Dinner 2h0'
  • Tuesday, 15 December 2015
    • 08:30 - 20:00
      • 08:30 Advanced SOC-FPGA trends 2h0'
        Speaker: Nizar Abdallah (SoC Products, Microsemi, CA, USA)
      • 10:30 Coffee Break 30'
      • 11:00 Standard Wishbone IP Interface 1h0'
        Speaker: Andres Cicuttin (ICTP Multidisciplinary Laboratory, Italy)
      • 12:00 Lunch 1h30'
      • 13:30 Serial communication using the RS-232 protocol (Lab. Tutorial) 2h0'
        Speaker: Hafeezullah Qazi
      • 15:30 Coffee Break 30'
      • 16:00 Laboratory Session 2h0'
        Speaker: Instructors
      • 18:00 Dinner 2h0'
  • Wednesday, 16 December 2015
    • 08:30 - 20:00
      • 08:30 Advanced SOC-FPGA trends 2h0'
      • 10:30 Coffee Break 30'
      • 11:00 FPGA Debugging 1h0'
        Speaker: Andres Cicuttin
      • 12:00 Lunch 1h30'
      • 13:30 Advanced SOC trends 2h0'
        Speaker: Paul Beckett (RMIT University, Melburne, Australia)
        Material: Slides
      • 15:30 Coffee Break 30'
      • 16:00 Digital Signal Processing in FPGA (Lab. Tutorial) 2h0'
        Speaker: Aamir Irshad (Optics Laboratories, Islamabad, Pakistan)
      • 18:00 Dinner 2h0'
  • Thursday, 17 December 2015
    • 08:30 - 20:00
      • 08:30 FPGAs as Hardware Accelerators 2h0'
        Speaker: Naeem Abbas (Pakistan National Engineering College, Pakistan)
      • 10:30 Coffee Break 30'
      • 11:00 Implementing video systems in FPGA 1h30'
        Speaker: Aamir Irshad
      • 12:30 Lunch 1h30'
      • 14:00 Laboratory Session 1h30'
        Speaker: Instructors
      • 15:30 Coffee Break 30'
      • 16:00 Laboratory Session 2h0'
        Speaker: Instructors
      • 18:00 Farewell Dinner 2h0'
  • Friday, 18 December 2015
    • 08:30 - 15:30
      • 08:30 Intro to Zynq architecture - PS and PL 2h0'
        Speaker: Sisterna Cristian Alejandro
      • 10:30 Coffee Break 30'
      • 11:00 Intro to Zedboard System Architecture 1h0'
        Speaker: Maria Liz Crespo
      • 12:00 Lunch 1h30'
      • 13:30 Closing Ceremony and Distribution of Diplomas of Attendance 2h0'