Description |
An ICTP Meeting
The school will cover key aspects of FPGA-based Systems-on-Chip (SoC-FPGA) and their applications to scientific instrumentation and reconfigurable computing, with emphasis in nuclear and particle physics experiments.
Modern nuclear and particle physics experiments require online data acquisition (DAQ) systems that process multiple and parallel signals coming from detectors and reduce both the data rate and the amount of data to be storage in disk for further offline analysis. These systems usually rely on the reconfigurable computing paradigm that combines software’s flexibility and hardware’s high performance using programmable computing fabrics such as SoC-FPGA.
Participants will be familiarized with professional software design tools and hardware platforms through tutorials and hands-on activities. They will do projects and build embedded instruments for nuclear applications and particle physics experiments. They will be also introduced to an open-source SoC-FPGA firmware framework, providing a well-tested interface with the control computer.
Topics:
Grants: A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee.
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Joint ICTP-IAEA School on Systems-on-Chip Based on FPGA for Scientific Instrumentation and Reconfigurable Computing | (smr 3891)
Go to day
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09:00 - 18:30
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09:00
Registration formalities
30'
Upon arrival, Visitors not staying in the ICTP Guest Houses, are kindly requested to complete registration formalities at the Adriatico Guest House (Lower level). The Registration Desk will be open from 9.00 to 9.30.
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09:30
Opening Remarks
15' (
Adriatico Guest House - Informatics Laboratory
)
Speaker: Maria Liz CRESPO (ICTP, Italy), Andres CICUTTIN (ICTP, Italy) -
09:45
School Outline
15'
Speaker: Maria Liz CRESPO (ICTP, Italy) Material: Slides -
10:00
Brief introduction from participants
15'
- 10:15 Coffee Break 30'
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10:45
FPGA and System-on-Chip (SoC) technology
1h45'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 12:30 Lunch Break 1h30'
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14:00
SoC Architecture and Design Methodology
2h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 16:00 Coffee Break 30'
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16:30
SoC Architecture and Design Methodology
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) -
17:30
Use of VMs and User environment
1h0'
Speaker: Luis Guillermo GARCÍA ORDÓÑEZ (ICTP, Italy) Material: Slides
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09:00
Registration formalities
30'
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09:00 - 18:30
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09:00 - 18:30
Location: Adriatico Guest House - Informatics Laboratory -
09:00
Zynq SoC: Evaluation and Development Board
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 10:00 Coffee Break 30'
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10:30
C for Embedded Systems
2h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 12:30 Lunch Break 1h30'
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14:00
Hardware and Software Interrupts on SoC
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) -
15:00
AXI Bus and Custom IP Cores
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 16:00 Coffee Break 30'
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16:30
Guide for Lab 1: Hello World + GPIO In/Out
15'
Speaker: Romina Soledad MOLINA (ICTP, Italy) Material: Slides -
16:45
Lab 1: Hello World + GPIO In/Out
1h45'
Speaker: Lab Tutors
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09:00
Zynq SoC: Evaluation and Development Board
1h0'
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09:00 - 18:30
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09:00 - 18:30
Location: Adriatico Guest House - Kastler Lecture Hall -
09:00
Fundamentals of VHDL (Hardware Description Language)
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) - 10:00 Coffee Break 30'
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10:30
VHDL for Synthesis
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides -
11:30
VHDL for Simulation
1h0'
Speaker: Cristian Alejandro SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 12:30 Lunch Break 1h30'
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14:00
Reconfigurable Virtual Instrumentation (RVI) based on SoC-FPGA
1h0'
Speaker: Andres CICUTTIN (ICTP, Italy) Material: Slides -
15:00
Guide for Lab 2: ComBlock (RVI Communication Block)
15' (
Adriatico Guest House - Informatics Laboratory
)
Speaker: Giovanni BALLINA ESCOBAR (ICTP, Italy) Material: Slides -
15:15
Lab 2: ComBlock + RTL instantiation
45'
Speaker: Lab Tutors - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0'
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09:00
Fundamentals of VHDL (Hardware Description Language)
1h0'
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19:00 - 20:30
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19:00
Welcome reception
1h30'
(
Adriatico Guest House Cafeteria
)
All participants are cordially invited to a Welcome reception
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19:00
Welcome reception
1h30'
(
Adriatico Guest House Cafeteria
)
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09:00 - 18:30
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09:00 - 18:30
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09:00
The Role of Programmable Hardware Acceleration in Virtualized Communications Networks
1h0' (
Adriatico Guest House - Kastler Lecture Hall
)
Speaker: Luca VALCARENGHI (Scuola Superiore Sant'Anna, Italy) Material: Slides - 10:00 Coffee Break 30'
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10:30
Real Time Operating System (FreeRTOS)
2h0'
Speaker: Heinrich Bartholomaus RONGEN (Juelich Gmbh, Germany) Material: Slides - 12:30 Lunch Break 2h0'
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14:00
FreeRTOS Tutorial
1h30'
Speaker: Heinrich Bartholomaus RONGEN (Juelich Gmbh, Germany) - 15:30 Coffee Break 30'
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16:00
Guide for Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
15' (
Adriatico Guest House - Informatics Laboratory
)
Speaker: Werner FLORIAN (ICTP, Italy) -
16:15
Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
2h15'
Speaker: Lab Tutors Material: Slides
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09:00
The Role of Programmable Hardware Acceleration in Virtualized Communications Networks
1h0' (
Adriatico Guest House - Kastler Lecture Hall
)
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09:00 - 18:30
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09:00 - 18:30
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09:00
The Open Standard RISC-V Architecture
1h0' (
Adriatico Guest House - Informatics Laboratory
)
Speaker: Fernando RINCON CALLE (University of Castilla-La Mancha, Spain) Material: Slides - 10:00 Coffee Break 30'
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10:30
High Level Synthesis (HLS)
2h0'
Speaker: Fernando RINCON CALLE (University of Castilla-La Mancha, Spain) Material: Slides - 12:30 Lunch Break 1h30'
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14:00
HLS Demo
1h0'
Speaker: Fernando RINCON CALLE (University of Castilla-La Mancha, Spain) Material: Slides -
15:00
Guide for Lab 4: SoC-FPGA DAQ system and TCL
15'
Speaker: Ivan MORALES ARGUETA (ICTP, Italy) Material: Slides -
15:15
Lab 4: SoC-FPGA DAQ system and TCL
45'
Speaker: Lab Tutors - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0'
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09:00
The Open Standard RISC-V Architecture
1h0' (
Adriatico Guest House - Informatics Laboratory
)
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09:00 - 18:30
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09:00 - 18:30
Location: Giambiagi Lecture Hall ( Informatics Laboratory (AGH) ) -
09:00
IAEA NSIL: Support to IAEA Member States and Recent Developments
1h0'
Speaker: Kalliopi KANAKI (IAEA, Austria) Material: Slides - 10:00 Coffee Break 30'
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10:30
FPGA for Accelerating Machine Learning Algorithms
1h0'
Speaker: Romina Soledad MOLINA (ICTP, Italy) Material: Slides -
11:30
Gaining a Deeper Insight Into the Project Lab Setup - System and Hardware Perspective
1h0'
Speaker: Nikola JOVALEKIC (Teledyne DALSA High Tech, The Netherlands) - 12:30 Lunch Break 1h30'
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14:00
Project 1: Digital Pulse Processing for Isotope Identification
1h0'
Speaker: Mladen BOGOVAC (IAEA, Austria) Material: Slides -
15:00
Guide for Project Lab 1.1: Pulse Acquisition and Detector Characterization
1h0'
Speaker: Ivan MORALES ARGUETA (ICTP, Italy) - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0' (
Adriatico Guest House - Informatics Laboratory
)
-
09:00
IAEA NSIL: Support to IAEA Member States and Recent Developments
1h0'
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09:00 - 18:30
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09:00 - 18:30
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09:00
The European Spallation Source Data Acquisition System
1h0'
Speaker: Richard HALL-WILTON (Bruno Kessler Foundation, Italy) Material: Slides - 10:00 Coffee Break 30'
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10:30
Switch Architectures for Data Center Networks
1h0'
Speaker: Piero CASTOLDI (Scuola Superiore Sant'Anna, Italy) Material: Slides -
11:30
Semiconductor Detectors, Fabrication Techniques, Quantum Detector Developments
1h0'
Speaker: Richard HALL-WILTON (Bruno Kessler Foundation, Italy) Material: Slides - 12:30 Group Photo 5'
- 12:35 Lunch Break 1h25'
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14:00
Project Lab 1.2: Digital Pulse Processing
1h0'
Speaker: Mladen BOGOVAC (IAEA, Austria) -
15:00
Guide for Project Lab 1.2: Digital Pulse Processing
15'
Speaker: Ivan MORALES ARGUETA (ICTP, Italy) -
15:15
Lab activities with tutors
45'
Speaker: Lab Tutors - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0'
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09:00
The European Spallation Source Data Acquisition System
1h0'
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09:00 - 18:30
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09:00 - 18:30
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09:00
FPGAs computing just right thanks to application-specific arithmetic
1h0'
Speaker: Florent Marie Paul DUPONT DE DINECHIN (National Institut of Applied Sciences, France) Material: Slides - 10:00 Coffee Break 30'
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10:30
FPGAs computing just right thanks to application-specific arithmetic
1h0'
Speaker: Florent Marie Paul DUPONT DE DINECHIN (National Institut of Applied Sciences, France) Material: Slides -
11:30
HyperFPGA: Experimental Infrastructure for Reconfigurable Supercomputing
1h0'
Speaker: Werner FLORIAN (ICTP, Italy) - 12:30 Lunch Break 1h30'
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14:00
Project Lab 1.3: Baseline Restorer and Pile-Up Rejection
1h0'
Speaker: Mladen BOGOVAC (IAEA, Austria) -
15:00
Lab activities with tutors
1h0'
Speaker: Lab Tutors - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0'
Speaker: Lab Tutors
-
09:00
FPGAs computing just right thanks to application-specific arithmetic
1h0'
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09:00 - 18:30
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09:00 - 18:30
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09:00
Academic Writing Strategy for Impacted Journal
1h0'
Speaker: Md Mamun Bin Ibne REAZ (Independent University Bangladesh) Material: Slides - 10:00 Coffee Break 30'
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10:30
The FloPoCo arithmetic core generator
1h0'
Speaker: Florent Marie Paul DUPONT DE DINECHIN (National Institut of Applied Sciences, France) -
11:30
Project 2: Digital Pulse Processing for X-ray Photon Detection and Energy Measurement
1h0'
Speaker: Andres CICUTTIN (ICTP, Italy) Material: Slides - 12:30 Lunch Break 1h30'
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14:00
Guide for Project Lab 2: Digital Pulse Processor (DPP)
30'
Speaker: Bruno VALINOTI (ICTP, Italy) -
14:30
Lab activities with tutors
1h30'
Speaker: Lab Tutors - 16:00 Coffee Break 30'
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16:30
Lab activities with tutors
2h0'
Speaker: Lab Tutors
-
09:00
Academic Writing Strategy for Impacted Journal
1h0'
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09:00 - 18:30
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09:00 - 16:00
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09:00
FPGAs and Quantum Computers
1h0'
Speaker: Agustin SILVA (National University of Mar del Plata, Argentina) - 10:00 Coffee Break 30'
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10:30
MLAB Visit
2h0'
- 12:30 Lunch Break 1h30'
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14:00
ICTP programmes and MLAB activities
1h0'
Speaker: Maria Liz CRESPO (ICTP, Italy) Material: Slides -
15:00
Distribution of Certificates and Closing Remarks
1h0'
-
09:00
FPGAs and Quantum Computers
1h0'
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09:00 - 16:00