Joint ICTP-IAEA School on Detector Signal Processing and Machine Learning for Scientific Instrumentation and Reconfigurable Computing | (smr 4110)
Starts 27 Oct 2025
Ends 7 Nov 2025
Central European Time
ICTP
Kastler Lecture Hall (AGH)
Adriatico Guest House
Riva Massimiliano e Carlotta, Grignano
I - 34151 Trieste (Italy)
An ICTP-IAEA meeting
The call for applications is open. Please click on 'Apply here' to submit your application.
The school will cover key aspects of detector signal processing and machine learning methods using FPGA-based systems-on-chip (SoC-FPGA) for scientific instrumentation and reconfigurable computing, with emphasis on applications in nuclear science and particle physics.
Modern nuclear and particle physics experiments require online data acquisition (DAQ) systems capable of processing multiple parallel signals from detectors, while reducing both the data rate and the volume of data stored for subsequent offline analysis. These systems typically rely on:
• Advanced digital pulse processing and machine learning methods for event detection and discrimination
• A reconfigurable computing paradigm that integrates the flexibility of software with the high performance of hardware in a single chip
Participants in the school will be introduced to open-source methods, software design tools, and hardware platforms through a combination of tutorials and hands-on lab sessions. They will design and develop embedded instruments using cost-effective detectors and SoC-FPGA devices for applications in nuclear science and particle physics.
Topics
Detector signal processing and event reconstruction
Machine learning and model compression for reconfigurable hardware accelerators
The reconfigurable computing paradigm
Systems-on-Chip: architecture and design methodology
Hardware description language (HDL) for FPGA design, modeling, and logic synthesis
Embedded C and high-level synthesis
Best practices in firmware and software development
Digital electronics for standard and modern sensors
Heterogeneous computing on MPSoC-FPGA
Grants: A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee.