Joint ICTP-IAEA School on Detector Signal Processing and Machine Learning for Scientific Instrumentation and Reconfigurable Computing | (smr 4110) (27 October 2025

Description

An ICTP-IAEA meeting

The school will cover key aspects of detector signal processing and machine learning methods using FPGA-based systems-on-chip (SoC-FPGA) for scientific instrumentation and reconfigurable computing, with emphasis on applications in nuclear science and particle physics.

Modern nuclear and particle physics experiments require online data acquisition (DAQ) systems capable of processing multiple parallel signals from detectors, while reducing both the data rate and the volume of data stored for subsequent offline analysis. These systems typically rely on:
• Advanced digital pulse processing and machine learning methods for event detection and discrimination
• A reconfigurable computing paradigm that integrates the flexibility of software with the high performance of hardware in a single chip

Participants in the school will be introduced to open-source methods, software design tools, and hardware platforms through a combination of tutorials and hands-on lab sessions. They will design and develop embedded instruments using cost-effective detectors and SoC-FPGA devices for applications in nuclear science and particle physics.

Topics

Detector signal processing and event reconstruction
Machine learning and model compression for reconfigurable hardware accelerators
The reconfigurable computing paradigm
Systems-on-Chip: architecture and design methodology
Hardware description language (HDL) for FPGA design, modeling, and logic synthesis
Embedded C and high-level synthesis
Best practices in firmware and software development
Digital electronics for standard and modern sensors
Heterogeneous computing on MPSoC-FPGA

Grants: A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee.

Material

Group Photo Week I Poster Preliminary List of Participants group photo

Joint ICTP-IAEA School on Detector Signal Processing and Machine Learning for Scientific Instrumentation and Reconfigurable Computing | (smr 4110)

Go to day

Monday, 27 October 2025

08:30 - 09:00 Registration Formalities

REGISTRATION: Upon arrival, Visitors not staying in the ICTP Guest Houses, are kindly requested to complete registration formalities at the Adriatico Guest House (Lower level). The Registration Desk will be open in the morning starting from 8:30.

09:00 - 18:00

09:00 Opening Remarks 10'

Speaker: Maria Liz CRESPO (ICTP, Italy)

09:10 School Outline 20'

Speaker:	Maria Liz CRESPO (ICTP, Italy)
Material:	Slides

09:30 Programmable System on Chip (PSoC) Architecture 1h0'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

10:30 Coffee Break 30'

11:00 Edge AI for the Internet of Things: Insights from Real-World Projects 45'

Speaker:	Dejan VUKOBRATOVIC (FTN-UNS, Serbia)
Material:	Slides

11:45 Development Board: Zynq SoC 45'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

12:30 Lunch Break 1h30'

14:00 C for Embedded Systems 1h0'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

15:00 Virtual Machine and User Environment 15'

Speaker: Maynor BALLINA (ICTP MLAB, Italy)
15:15 Guide for Lab 1 - Getting Started with SoC 15'

Speaker: Maynor BALLINA (ICTP MLAB, Italy)
15:30 Lab 1 with tutors 30'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Lab 1 with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Tuesday, 28 October 2025

09:00 - 18:00

09:00 Semiconductors and Collaboration: Building Pathways for Innovation and Talent 45'

Speaker:	Razaidi Bin Hussin (Universiti Malaysia Perlis, Malaysia)
Material:	Slides

09:45 SoC: A Practical Implementation Overview on Intelligent Neurosystems 30'

Speaker:	Sawal Hamid Ali (Universiti Kebangsaan Malaysia, Malaysia)
Material:	Slides

10:15 Coffee Break 30'

10:45 Introduction to AI-Enabled Semantic and Goal-Oriented Communications for the Internet of Things 1h0'

Speaker:	Dejan VUKOBRATOVIC (FTN-UNS, Serbia)
Material:	Slides

11:45 Hardware Description Language for Reconfigurable Instrumentation 45'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

12:30 Lunch Break 1h30'
14:00 Hardware-Software Co-Design 45'

Speaker: Cristian SISTERNA (IDIA, Argentina)
14:45 Guide for Lab 2 - Reconfigurable Instrumentation on SoC-FPGA 15'

Speaker: Maynor BALLINA (ICTP MLAB, Italy)
15:00 Lab 2 with tutors 1h0'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Lab 2 with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Wednesday, 29 October 2025

09:00 - 18:00

09:00 Introduction to Machine Learning and Edge AI 1h0'

Speaker:	Romina MOLINA (ICTP MLAB, Italy)
Material:	Slides

10:00 Coffee Break 30'

10:30 When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part I 1h0'

Speaker:	Vukan NINKOVIC (Technical Sciences University of Novi Sad, Serbia)
Material:	Slides

11:30 Peripheral Interfaces & IP Integration 1h0'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

12:30 Lunch Break 1h30'
14:00 Embedded Real-Time Operating System 1h0'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
15:00 Guide for Lab 3 - SoC-FPGA Development Framework 15'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
15:15 Lab 3 with tutors 45'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Lab 3 with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Thursday, 30 October 2025

09:00 - 18:00

09:00 High-Level Synthesis (HLS) – Part I 1h0'

Speaker:	Fernando RINCON (University of Castilla-La Mancha, Spain)
Material:	Slides

10:00 Coffee Break 30'

10:30 When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part II 1h0'

Speaker:	Vukan NINKOVIC (Technical Sciences University of Novi Sad, Serbia)
Material:	Slides

11:30 Fundamentals of Applied Machine Learning 1h0'

Speaker:	Romina MOLINA (ICTP MLAB, Italy)
Material:	Slides

12:30 Group Photo 5'
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Group Photo
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12:35 Lunch Break 1h25'
14:00 Lab 4.1: Training Machine Learning Models 1h0'
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Laboratory:  Lecturers and Lab Tutors
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15:00 Model Optimization and Compression Techniques 1h0'

Speaker:	Romina MOLINA (ICTP MLAB, Italy)
Material:	Slides

16:00 Coffee Break 15'
16:15 Lab 4.2: Applying Model Compression Techniques 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Friday, 31 October 2025

09:00 - 18:00

09:00 High-Level Synthesis (HLS) – Part II 1h0'

Speaker: Fernando RINCON (University of Castilla-La Mancha, Spain)
10:00 Coffee Break 30'

10:30 Integrating Intelligence in 5G: How ML and AI Are Shaping 5G Networks? 1h0'

Speaker:	Dejan VUKOBRATOVIC (FTN-UNS, Serbia)
Material:	Slides

11:30 Using FPGAs to Accelerate Machine Learning Algorithms 1h0'

Speaker:	Romina MOLINA (ICTP MLAB, Italy)
Material:	Slides

12:30 Lunch Break 1h30'
14:00 Edge AI Applications on FPGA-Based Systems 1h0'

Speaker: Romina MOLINA (ICTP MLAB, Italy)
15:00 Lab 5.1: Integrating ML Models with HLS4ML for Hardware Synthesis 1h0'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Lab 5.2: Deploying Machine Learning Models on SoC-FPGA 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Monday, 3 November 2025

09:00 - 18:00

09:00 The Open Standard RISC-V Architecture - Part I 1h0'

Speaker:	Fernando RINCON (University of Castilla-La Mancha, Spain)
Material:	Slides

10:00 Coffee Break 30'
10:30 The Open Standard RISC-V Architecture - Part II 1h0'

Speaker: Fernando RINCON (University of Castilla-La Mancha, Spain)

11:30 Digital Pulse Processing for Isotope Identification 1h0'

Speaker:	Mladen BOGOVAC (IAEA, Austria)
Material:	Slides

12:30 Lunch Break 1h30'

14:00 Pulse Acquisition and Detector Characterization 45'

Speaker:	Mladen BOGOVAC (IAEA, Austria)
Material:	Slides

14:45 Guide for Lab 6: Pulse Acquisition and Detector Characterization 15'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
15:00 Lab 6 with tutors 1h0'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Lab 6 with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Tuesday, 4 November 2025

09:00 - 18:15

09:00 Design Methodology for FPGA-based System on Chip 1h0'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

10:00 Coffee Break 30'

10:30 Digital Pulse Processing for X-ray Photon Detection and Energy Measurement 1h0'

Speaker:	Andres CICUTTIN (ICTP, Italy)
Material:	Slides

11:30 Digital Pulse Processor: Main Functional Blocks - Part I 1h0'

Speaker: Mladen BOGOVAC (IAEA, Austria)
12:30 Lunch Break 1h30'
14:00 Digital Pulse Processor: Main Functional Blocks - Part II 30'

Speaker: Mladen BOGOVAC (IAEA, Austria)
14:30 Guide for Lab 7: Digital Pulse Processor (DPP) 15'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
14:45 Lab 7 with tutors 1h15'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee break 15'
16:15 Lab 7 with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Wednesday, 5 November 2025

09:00 - 18:00

09:00 Advanced SoC-FPGA Topics 1h0'

Speaker:	Cristian SISTERNA (IDIA, Argentina)
Material:	Slides

10:00 Group Photo 5'
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Group Photo at Adriatico Terrace
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10:05 Coffee Break 25'

10:30 Embedded Linux on SoC-FPGA 1h0'

Speaker:	Fabian CASTANO (Universidad de Antioquia, Colombia)
Material:	Slides

11:30 Handling High Event Rates and Pile-Up - Part I 1h0'

Speaker: Mladen BOGOVAC (IAEA, Austria)
12:30 Lunch break 1h30'
14:00 Handling High Event Rates and Pile-Up - Part II 30'

Speaker: Mladen BOGOVAC (IAEA, Austria)
14:30 Guide for Final Project - Part I 15'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
14:45 Project Lab with Tutors 1h15'
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Laboratory: Lecturers and Lab Tutors
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16:00 Coffee break 15'
16:15 Project Lab with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Thursday, 6 November 2025

09:00 - 18:00

09:00 Hog: An Open-Source Tool for Managing HDL Repositories on Git 1h0'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
10:00 Coffee Break 30'

10:30 High Event-Rate Discrimination on Mixed Radiation Fields with Machine Learning 1h0'

Online

Speaker:	Ivan MORALES (IAEA, Austria)
Material:	Slides

11:30 End-to-End Dataset Generation for Machine Learning 1h0'

Speakers: Mayor BALLINA, Romina MOLINA (ICTP MLAB, Italy)
12:30 Lunch Break 1h30'
14:00 Integrating Machine Learning into Digital Pulse Processing 30'

Speaker: Maynor BALLINA, Romina MOLINA (ICTP MLAB, Italy)
14:30 Guide for Final Project - Part II 15'
14:45 Project lab with tutors 1h15'
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Laboratory:  Lecturers and Lab Tutors
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16:00 Coffee Break 15'
16:15 Project Lab with tutors 1h45'
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Laboratory:  Lecturers and Lab Tutors
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Friday, 7 November 2025

09:00 - 14:30

09:00 Green Intelligence at the Edge: Sustainable Hardware for AI 1h0'

Speaker: Mamun Bin Reaz (Independent University, Bangladesh Bashundhara, Bangladesh)
10:00 Coffee Break 30'
10:30 HyperFPGA: Heterogeneous Computing on MPSoC-FPGA at ICTP 30'

Speaker: Maynor BALLINA (ICTP MLAB, Italy)
11:00 ICTP-IAEA MA-XRF Scanner 30'

Speaker: Luis GARCIA (ICTP MLAB, Italy)
11:30 IAEA Programmes & NSIL Activities 30'

Speaker: Kalliopi Kanaki, Mladen BOGOVAC (IAEA, Austria)

12:00 ICTP Programmes & MLab Activities 30'

Speaker:	Maria Liz CRESPO (ICTP, Italy)
Material:	Slides

12:30 Lunch Break 1h30'
14:00 Distribution of Certificates and Closing Remarks 30'

Speaker: Maria Liz CRESPO (ICTP, Italy)