Scientific Calendar Event



Description
An ICTP-IAEA Meeting in person.

The school will cover key aspects of fully-programmable Systems-On-Chip (SoC) technology and its applications to scientific instrumentation. The aim is to familiarize participants with professional software design tools and hardware platforms through tutorials and project examples in the field of nuclear applications.  

Traditional FPGA devices have been utilized in many nuclear instruments for the past few decades, allowing multiple and parallel processing of signals from radiation detectors and other sensors. These features make instruments more compact by reducing number of required processors and minimizing complexity of analog electronics for signal processing. Modern SoC integrate the software programmability of processors with the hardware configurability of FPGAs in a single chip.

In the first two weeks, participants will carry out hands-on activities with software automation tools and hardware setups. Programming at FPGA level as well as processor level will be performed and interfacing with a wide variety of modular platforms will be undertaken. In the third week, participants will do projects and build embedded instruments for nuclear applications. In addition, they will be introduced to an open-source SoC-FPGA firmware platform, providing a well-tested interface with the control computer.

Topics:
  • Systems-on-Chip: Architecture and Design Methodology
  • Hardware/Software Interface
  • Design Automation Tools
  • VHDL for FPGA Design, Modeling, and Logic Synthesis
  • Embedded C Language Programming
  • High Level Synthesis
  • Real-time Data Acquisition, Processing, and Transmission
  • Digital Pulse Processing Techniques
  • FPGA for Acceleration of AI Algorithms
  • Laboratory Sessions for Hands-On Training and Experimentation

Grants: A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee.
 

Go to day
  • Monday, 14 November 2022
    • 09:00 - 09:30
      • 09:00 Registration formalities 30' ( Adriatico Guest House - (Lower Level 1) )
        REGISTRATION: Upon arrival, Visitors not staying in the ICTP Guest Houses, are kindly requested to complete registration formalities at the Adriatico Guesthouse, Registration Desk (Lower level) from 9.00 till 9.30.
    • 09:30 - 12:30
      • 09:30 Welcome to the School 10'
        Speaker: Maria Liz CRESPO (ICTP, Italy), Kalliopi KANAKI (IAEA, Austria), Andres CICUTTIN, (ICTP, Italy), Mladen BOGOVAC (IAEA, Austria)
      • 09:40 School Outline 10'
        Speaker: Maria Liz CRESPO (ICTP, Italy)
        Material: Slides
      • 09:50 Brief introduction from participants 10'
      • 10:00 Coffee break 30'
      • 10:30 Logic design and finite state machines 1h0'
        Speaker: Pirouz BAZARGAN SABET (Sorbonne University, France)
        Material: Slides
      • 11:30 FPGA and System-on-Chip (SoC) technology 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
        Material: Slides
    • 14:00 - 17:30
      • 14:00 Digital numbers representation: fixed point vs floating point 1h0'
        Speaker: Pirouz BAZARGAN SABET (Sorbonne University, France)
      • 15:00 SoC architecture and design methodology 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
        Material: Slides
      • 16:00 Coffee break 30'
      • 16:30 SoC architecture and design methodology (cont.) 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
  • Tuesday, 15 November 2022
    • 09:00 - 12:30
      • 09:00 Digital Arithmetic 1h0'
        Speaker: Pirouz BAZARGAN SABET (Sorbonne University, France)
      • 10:00 Coffee break 30'
      • 10:30 Zynq-7000 SoC: Evaluation and Development Board 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
        Material: Slides
      • 11:30 C for Embedded Systems 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 C for Embedded Systems (cont.) 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 15:00 Hardware and Software Interrupts on SoC 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 16:00 Coffee break 30'
      • 16:30 AXI Bus and Custom IP Cores 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 17:30 Connectivity testing for lab activities 30' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy)
  • Wednesday, 16 November 2022
    • 09:00 - 12:30
      • 09:00 Floating point operations: square root and division 1h0'
        Speaker: Pirouz BAZARGAN SABET (Sorbonne University, France)
      • 10:00 Coffee break 30'
      • 10:30 Programmable hardware acceleration in Communication Networks 1h0'
        Speaker: Luca VALCARENGHI (Scuola Superiore Sant'Anna, TeCIP Institute, Italy)
        Material: Slides
      • 11:30 Quantization in Neural Networks: Advantages and Limitations 1h0'
        Speaker: Emilio PAOLINI (Scuola Superiore Sant'Anna, TeCIP Institute, Italy)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 Fundamentals of VHDL (Hardware Description Language) 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 15:00 VHDL for Synthesis 1h0'
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 16:00 Coffee break 30'
      • 16:30 Introduction to Lab Activities 30' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy)
      • 17:00 Lab 1: Hello World 1h0' ( Adriatico Guest House - Infolab )
  • Thursday, 17 November 2022
    • 09:00 - 12:30
      • 09:00 The role of programmable hardware acceleration in the edge-cloud continuum 1h0'
        Speaker: Luca VALCARENGHI (Scuola Superiore Sant'Anna, TeCIP Institute, Italy)
        Material: Slides
      • 10:00 Coffee break 30'
      • 10:30 New SoC platforms for Al and Algorithm Acceleration 2h0'
        Speaker: Gustavo SUTTER CAPRISTO (Universidad Autonoma de Madrid Tecnologia Electronica y de las Comunicaciones, Spain)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 High Level Synthesis (HLS) 2h0'
        Speaker: Fernando RINCON CALLE (Universidad de Castilla la Mancha, Spain)
        Material: Slides
      • 16:00 Coffee break 30'
      • 16:30 Guide for Lab 2: GPIO In/Out 30' ( Adriatico Guest House - Infolab )
        Speaker: Maynor BALLINA ESCOBAR (Universidad de San Carlos de Guatemala, Guatemala)
      • 17:00 Lab 2: GPIO In/Out 1h0' ( Adriatico Guest House - Infolab )
    • 19:00 - 20:30
      Location: Adriatico Guest House Cafeteria
      • 19:00 Welcome Reception 1h30'
         All participants are cordially invited to the Welcome Reception.
  • Friday, 18 November 2022
    • 09:00 - 12:30
      • 09:00 New SoC platforms for Al and Algorithm Acceleration (cont.) 1h0'
        Speaker: Gustavo SUTTER CAPRISTO (Universidad Autonoma de Madrid Tecnologia Electronica y de las Comunicaciones, Spain)
      • 10:00 Coffee break 30'
      • 10:30 HLS Tutorial 2h0' ( Adriatico Guest House - Infolab )
        Speaker: Fernando RINCON CALLE (Universidad de Castilla la Mancha, Spain)
    • 14:00 - 18:00
      • 14:00 VHDL for Simulation (Testbench) 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Instituto de Investigaciones Antisismicas, Argentina)
      • 15:00 Lab 3: Custom IP and VHDL 1h0' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Monday, 21 November 2022
    • 09:00 - 12:30
      • 09:00 Computer vision on FPGA 1h0'
        Speaker: SAWAL HAMID BIN MD ALI (University Kebangsaan Malaysia, Malaysia)
        Material: Slides
      • 10:00 Coffee break 30'
      • 10:30 BondMachine, a mouldable computer architecture 2h0'
        Speaker: Mirko MARIOTTI (University of Perugia, Italy)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 Guide for Lab 4: External Interrupt Sw/Hw 30' ( Adriatico Guest House - Infolab )
        Speaker: Ivan MORALES ARGUETA (ICTP, Italy)
      • 14:30 Lab 4: External Interrupt Sw/Hw 1h30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Tuesday, 22 November 2022
    • 09:00 - 12:30
      • 09:00 BondMachine, a mouldable computer architecture (cont.) 1h0'
        Speaker: Mirko MARIOTTI (University of Perugia, Italy)
      • 10:00 Coffee break 30'
      • 10:30 Real Time Operating System (FreeRTOS) 2h0'
        Speaker: Heinrich RONGEN (Forschungszentrum Juelich Gmbh ZEA2 Electronic Systems, Germany)
    • 14:00 - 18:00
      • 14:00 Guide for Lab 5: Direct Memory Access (DMA) 30' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy)
      • 14:30 Lab 5: Direct Memory Access (DMA) 1h30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Wednesday, 23 November 2022
    • 09:00 - 12:30
      • 09:00 FPGAs computing just right thanks to application-specific arithmetic 1h0'
        Speaker: Florent DUPONT DE DINECHIN (National Institut of Applied Sciences, France)
        Material: Slides
      • 10:00 Coffee break 30'
      • 10:30 FPGAs computing just right thanks to application-specific arithmetic (cont.) 1h0'
        Speaker: Florent DUPONT DE DINECHIN (National Institut of Applied Sciences, France)
        Material: Slides
      • 11:30 FPGA for Accelerating Machine Learning Algorithms 1h0'
        Speaker: Romina MOLINA (University of Trieste, Italy)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 Reconfigurable Virtual Instrumentation (RVI) based on SoC-FPGA 1h0'
        Speaker: Andres CICUTTIN (ICTP, Italy)
        Material: Slides
      • 15:00 The RVI communication block: ComBlock 30' ( Adriatico Guest House - Infolab )
        Speaker: Werner FLORIAN (ICTP, Italy)
      • 15:30 Lab 6: ComBlock 30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Thursday, 24 November 2022
    • 09:00 - 12:30
      • 09:00 The FloPoCo arithmetic core generator 1h0'
        Speaker: Florent DUPONT DE DINECHIN (National Institut of Applied Sciences, France)
      • 10:00 Coffee break 30'
      • 10:30 The FloPoCo arithmetic core generator (cont.) 1h0'
        Speaker: Florent DUPONT DE DINECHIN (National Institut of Applied Sciences, France)
      • 11:30 FreeRTOS Tutorial 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Heinrich RONGEN (Forschungszentrum Juelich Gmbh ZEA2 Electronic Systems, Germany)
    • 14:00 - 18:00
      • 14:00 FreeRTOS Tutorial 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Heinrich RONGEN (Forschungszentrum Juelich Gmbh ZEA2 Electronic Systems, Germany)
      • 15:00 SoC-FPGA Development Framework: UDMA & CLI 30' ( Adriatico Guest House - Infolab )
        Speaker: Werner FLORIAN (ICTP, Italy)
      • 15:30 Lab 7: UDMA & CLI 30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Friday, 25 November 2022
    • 09:00 - 12:30
      • 09:00 High Channel Count for Electrophysiology (HiCCE) 1h0'
        Speaker: Kasun MANNATUNGA (University of Moratuwa, Sri Lanka)
        Material: Slides
      • 10:00 Coffee break 30'
      • 10:30 Academic Writing Strategy for Impacted Journal 2h0'
        Speaker: Mamun Bin Ibne REAZ (Universiti Kebangsaan Malaysia, Malaysia)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 Guide for Lab 8: SoC-FPGA DAQ System and TCL 30' ( Adriatico Guest House - Infolab )
        Speaker: Ivan MORALES ARGUETA (ICTP, Italy)
      • 14:30 Lab 8: ADC-DAC loopback and TCL 1h30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Lab activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Monday, 28 November 2022
    • 09:00 - 12:30
      • 09:00 Reinforcement Learning and Quantum Computing 1h0'
        Speaker: Agustin SILVA (National University of Mar del Plata, Argentina)
        Material: Slides
      • 10:00 Coffee break 30'
      • 10:30 Project 1 - Data Acquisition System based on FPGA for Ionization Radiation Measurement 1h0'
        Speaker: Mladen BOGOVAC (IAEA, Austria)
      • 11:30 Project 2 - Digital pulse processing for X-ray photon detection and energy measurement 1h0'
        Speaker: Andres CICUTTIN (ICTP, Italy)
        Material: Slides
    • 14:00 - 18:00
      • 14:00 Custom-designed Data Acquisition System based on FPGA for Ionization Radiation Measurement 1h0'
        Speaker: Nikola JOVALEKIC (Teledyne DALSA, Netherlands)
      • 15:00 Open-source Toolchain for ARM-based Microcontrollers: Motivation and Methodology 1h0'
        Speaker: Nikola JOVALEKIC (Teledyne DALSA, Netherlands)
      • 16:00 Coffee break 30'
      • 16:30 GIT for Open Science 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Werner FLORIAN (ICTP, Italy)
        Material: Slides
      • 17:30 Introduction to Projects Activities 30' ( Adriatico Guest House - Infolab )
        Speaker: Maria Liz CRESPO (ICTP, Italy)
        Material: Slides
  • Tuesday, 29 November 2022
    • 09:00 - 12:30 Data Acquisition and Processing Systems for Radiation Detectors
      • 09:00 Project-1 - Advanced Digital Pulse Processing (DPP) Algorithms for Radiation Detectors 1h0'
        Speaker: Mladen BOGOVAC (IAEA, Austria)
      • 09:00 Project-2 - SoC-FPGA Data Acquisition and Guide for Lab 2.1 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy)
      • 10:00 Coffee break 30'
      • 10:30 Project activities with tutors 2h0' ( Adriatico Guest House - Infolab )
    • 14:00 - 18:00 Data Acquisition and Processing Systems for Radiation Detectors
      • 14:00 Project 1 - Deep Dive: Custom-Designed System for Advanced DPP for Radiation Detectors 1h0'
        Speaker: Nikola JOVALEKIC (Teledyne DALSA, Netherlands)
      • 15:00 Project activities with tutors 1h0' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Project 1 - Software configuration (bring-up) of the custom-designed hardware platform for DPP and Guide for Lab 1.1 30'
        Speaker: Nikola JOVALEKIC (Teledyne DALSA, Netherlands)
      • 17:00 Project activities with tutors 1h0' ( Adriatico Guest House - Infolab )
  • Wednesday, 30 November 2022
    • 09:00 - 12:30 Data Acquisition and Processing Systems for Radiation Detectors
      • 09:00 Project-2 - SoC-FPGA Digital Pulse Processor and Guide for Lab 2.2 1h0'
        Speaker: Bruno VALINOTI (ICTP, Italy)
      • 10:00 Coffee break 30'
      • 10:30 Project activities with tutors 2h0' ( Adriatico Guest House - Infolab )
    • 14:00 - 18:00 Data Acquisition and Processing Systems for Radiation Detectors
      • 14:00 Project 1 - Advanced Configuration of the FPGA on the custom-designed platform for DPP and Guide for Lab 1.2 30'
        Speaker: Ivan MORALES ARGUETA (ICTP, Italy)
      • 14:30 Project activities with tutors 1h30' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Project activities with tutors 1h30' ( Adriatico Guest House - Infolab )
  • Thursday, 1 December 2022
    • 09:00 - 12:30 Data Acquisition and Processing Systems for Radiation Detectors
      • 09:00 Project 1 - FPGA Peripheral Configuration and Microblaze Soft Core Design on Custom-Designed Hardware Platform for DPP and Guide for Lab 1.3 1h0'
        Speaker: Mladen BOGOVAC (IAEA, Austria)
      • 09:00 Project-2: SoC-FPGA Data Acquisition and Digital Pulse Processing for Radiation Detectors and Guide for Lab 2.3 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy), Bruno VALINOTI (ICTP, Italy), Werner FLORIAN (ICTP, Italy)
      • 10:00 Group Photo 5'
      • 10:05 Coffee break 25'
      • 10:30 Project activities with tutors 2h0' ( Adriatico Guest House - Infolab )
    • 14:00 - 17:30 Data Acquisition and Processing Systems for Radiation Detectors
      • 14:00 Project activities with tutors 2h0' ( Adriatico Guest House - Infolab )
      • 16:00 Coffee break 30'
      • 16:30 Project 1 - Demo: Integration of the DPP Platform with Advanced Processing Algorithm and Live Measurements 1h0'
        Speaker: Mladen BOGOVAC (IAEA, Austria), Nikola JOVALEKIC (Teledyne DALSA, Netherlands), Ivan MORALES ARGUETA (ICTP, Italy)
      • 16:30 Project 2 - Demo: SoC-FPGA Data Acquisition, Digital Pulse Processing and Live Measurements 1h0' ( Adriatico Guest House - Infolab )
        Speaker: Luis GARCIA ORDONEZ (ICTP, Italy), Bruno VALINOTI (ICTP, Italy), Werner FLORIAN (ICTP, Italy)
    • 19:30 - 21:30
      • 19:30 Social Dinner 2h0'
        All participants are cordially invited to the Social dinner
  • Friday, 2 December 2022
    • 09:00 - 12:30
      • 09:00 Project presentations from participants groups 1h0'
      • 10:00 Coffee break 30'
      • 10:30 Project presentations from participants groups 2h0'
    • 14:00 - 17:00
      • 14:00 IAEA NSIL: Support to IAEA Member States and Recent Developments 1h0'
        Speaker: Kalliopi KANAKI (IAEA, Austria)
      • 15:00 ICTP programmes and MLAB activities 1h0'
        Speaker: Maria Liz CRESPO (ICTP, Italy)
        Material: Slides
      • 16:00 Coffee break 30'
      • 16:30 Participants Awards, Distribution of Certificates, and Closing Remarks 30'
        Speaker: Maria Liz CRESPO (ICTP, Italy), Kalliopi KANAKI (IAEA, Austria), Andres CICUTTIN, (ICTP, Italy), Mladen BOGOVAC (IAEA, Austria)