ICTP-INFN Microprocessor Laboratory ICTP-KNUST Regional Microelectronics Workshop on FPGA and VHDL for Research and Training in Africa | (smr 1691) (25 July 2005

Administration

Description

PLEASE NOTE:
Scientists consulting the WEB site of the Centre can use the account: 
sis_update@ictp.it 
to inform us of changes to their personal data, as published on the WEB SIS (Scientific Information System database).

VENUE:
KNUST, Kumasi, Ghana

LOCAL CONTACT:
fka@ghana.com (Francis K. Allotey)
debrahoa@yahoo.co.uk (Owusu Debrah)
PhilipOkyere@aol.com (Philip Okyere)

Material

announcement application form list of participants related links

ICTP-INFN Microprocessor Laboratory ICTP-KNUST Regional Microelectronics Workshop on FPGA and VHDL for Research and Training in Africa | (smr 1691)

Go to day

Monday, 25 July 2005
- 09:00 - 10:00 REGISTRATION
  - 09:00 REGISTRATION 1h0'
- 10:00 - 12:30 OPENING CEREMONY
  - 10:00 OPENING CEREMONY 2h30'
    
    Speaker: Kwesi A. Andam, Francis K.A. Allotey, Nizar Abdallah, Andres Cicuttin
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Course Ovierview
  - 14:30 Course Ovierview 1h30'
    
    Speaker: Nizar Abdallah
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 18:00 Synthesis II - Introduction to VHDL
  - 16:30 Synthesis II - Introduction to VHDL 1h30'
    
    Speaker: Nizar Abdallah
- 18:00 - 20:00 Laboratory
  - 18:00 Laboratory 2h0'
Tuesday, 26 July 2005
- 09:00 - 10:30 Synthesis III - Advanced VHDL
  - 09:00 Synthesis III - Advanced VHDL 1h30'
    
    Speaker: Nizar Abdallah
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Programmable Logic & FPGA Architecture
  - 11:00 Programmable Logic & FPGA Architecture 1h30'
    
    Speaker: Nizar Abdallah
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Introduction to Digital Design
  - 14:30 Introduction to Digital Design 1h30'
    
    Speaker: Julio Dondo Gazzano
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 18:00 Introduction to Actel Products
  - 16:30 Introduction to Actel Products 1h30'
    
    Speaker: Nizar Abdallah
Wednesday, 27 July 2005
- 09:00 - 10:30 Actel ProASIC Plus FPGA Architecture
  - 09:00 Actel ProASIC Plus FPGA Architecture 1h30'
    
    Speaker: Nizar Abdallah
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Combinatorial Circuits
  - 11:00 Combinatorial Circuits 1h30'
    
    Speaker: Julio Dondo Gazzano
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Libero IDE Overview and Design Flow
  - 14:30 Libero IDE Overview and Design Flow 1h30'
    
    Speaker: Nizar Abdallah
- 16:00 - 17:30 Design Entry
  - 16:00 Design Entry 1h30'
    
    Speaker: Nizar Abdallah
- 17:30 - 18:00 Coffee Break
  - 17:30 Coffee Break 30'
- 18:00 - 20:00 Laboratory
  - 18:00 Laboratory 2h0'
Thursday, 28 July 2005
- 09:00 - 10:30 Design Verification and Timing Concepts
  - 09:00 Design Verification and Timing Concepts 1h30'
    
    Speaker: Nizar Abdallah
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Sequential circuits
  - 11:00 Sequential circuits 1h30'
    
    Speaker: Julio Dondo Gazzano
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Functional Simulation Synthesis
  - 14:30 Functional Simulation Synthesis 1h30'
    
    Speaker: Nizar Abdallah
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'
Friday, 29 July 2005
- 09:00 - 10:30 Sytstem-on-Chip Concepts
  - 09:00 Sytstem-on-Chip Concepts 1h30'
    
    Speaker: Nizar Abdallah
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Introduction to Digital Arithmetic
  - 11:00 Introduction to Digital Arithmetic 1h30'
    
    Speaker: Julio Dondo Gazzano
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Place & Route
  - 14:30 Place & Route 1h30'
    
    Speaker: Nizar Abdallah
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 18:00 Selected Topics on FPGA Design and Logic Synthesis I
  - 16:30 Selected Topics on FPGA Design and Logic Synthesis I 1h30'
    
    Speaker: Andres Cicuttin
- 18:00 - 20:00 Laboratory
  - 18:00 Laboratory 2h0'
Monday, 1 August 2005
- 09:00 - 10:30 Introduction to Fourier Theory
  - 09:00 Introduction to Fourier Theory 1h30'
    
    Speaker: Marcelo Magnasco
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Digital Signal Processing I
  - 11:00 Digital Signal Processing I 1h30'
    
    Speaker: Marcelo Magnasco
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Selected Topics on FPGA Design and Logic Synthesis II
  - 14:30 Selected Topics on FPGA Design and Logic Synthesis II 1h30'
    
    Speaker: Andres Cicuttin
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'
Tuesday, 2 August 2005
- 09:00 - 10:30 Digital Signal Processing II
  - 09:00 Digital Signal Processing II 1h30'
    
    Speaker: Marcelo Magnasco
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Laboratory
  - 11:00 Laboratory 1h30'
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Laboratory
  - 14:30 Laboratory 1h30'
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'
Wednesday, 3 August 2005
- 09:00 - 10:30 Digital Signal Processing III
  - 09:00 Digital Signal Processing III 1h30'
    
    Speaker: Marcelo Magnasco
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Laboratory
  - 11:00 Laboratory 1h30'
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Laboratory
  - 14:30 Laboratory 1h30'
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'
Thursday, 4 August 2005
- 09:00 - 10:30 Laboratory
  - 09:00 Laboratory 1h30'
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Laboratory
  - 11:00 Laboratory 1h30'
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Laboratory
  - 14:30 Laboratory 1h30'
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'
Friday, 5 August 2005
- 09:00 - 10:30 Laboratory
  - 09:00 Laboratory 1h30'
- 10:30 - 11:00 Coffee Break
  - 10:30 Coffee Break 30'
- 11:00 - 12:30 Laboratory
  - 11:00 Laboratory 1h30'
- 12:30 - 14:30 Lunch Break
  - 12:30 Lunch Break 2h0'
- 14:30 - 16:00 Laboratory
  - 14:30 Laboratory 1h30'
- 16:00 - 16:30 Coffee Break
  - 16:00 Coffee Break 30'
- 16:30 - 20:00 Laboratory
  - 16:30 Laboratory 3h30'