Final List Participants
First ICTP Regional Microelectronics Workshop and Training on VHDL for Hardware Synthesis and FPGA Design in Asia-Pacific | (smr 1977)
Go to day
-
-
08:15 - 09:30
REGISTRATION AND ADMIN FORMALITIES
-
08:15
REGISTRATION AND ADMIN FORMALITIES
1h15'
-
08:15
REGISTRATION AND ADMIN FORMALITIES
1h15'
-
09:30 - 10:15
Altera-MDEC FPGA Education Launch
-
09:30
Altera-MDEC FPGA Education Launch
45'
-
09:30
Altera-MDEC FPGA Education Launch
45'
-
10:15 - 10:30
Break
- 10:15 Break 15'
-
10:30 - 11:30
Introduction
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10:30
Introduction
1h0'
-
10:30
Introduction
1h0'
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11:30 - 11:45
Break
- 11:30 Break 15'
-
11:45 - 13:00
Opening Ceremony
-
11:45
Opening Ceremony
1h15'
-
11:45
Opening Ceremony
1h15'
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13:00 - 15:00
Opening Lunch
- 13:00 Opening Lunch 2h0'
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15:00 - 15:30
Course Overview
-
15:00
Course Overview
30'
Speaker: Nizar Abdallah, Andres Cicuttin (ACTEL, ICTP)
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15:00
Course Overview
30'
-
15:30 - 16:30
Effective FPGA/VLSI Education Techniques
-
15:30
Effective FPGA/VLSI Education Techniques
1h0'
Speaker: Stephen Brown (Director, Altera University Programme)
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15:30
Effective FPGA/VLSI Education Techniques
1h0'
-
16:30 - 17:00
Break
- 16:30 Break 30'
-
17:00 - 18:00
Introduction to FPGA Synthesis, Introduction to VHDL.
-
17:00
Introduction to FPGA Synthesis, Introduction to VHDL.
1h0'
Speaker: Nizar Abdallah
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17:00
Introduction to FPGA Synthesis, Introduction to VHDL.
1h0'
-
18:00 - 19:00
Introduction to Digital Design (Boolean logic)
-
18:00
Introduction to Digital Design (Boolean logic)
1h0'
Speaker: Pirouz Bazargan-Sabet
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18:00
Introduction to Digital Design (Boolean logic)
1h0'
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20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
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08:15 - 09:30
REGISTRATION AND ADMIN FORMALITIES
-
-
09:30 - 10:30
Introduction to ACETEL Products. Libero IDE Overview and Design flow
-
09:30
Introduction to ACETEL Products. Libero IDE Overview and Design flow
1h0'
Speaker: Nizar Abdallah
-
09:30
Introduction to ACETEL Products. Libero IDE Overview and Design flow
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Synthesis I - Introduction to VHDL
-
11:00
Synthesis I - Introduction to VHDL
1h0'
Speaker: Nizar Abdallah
-
11:00
Synthesis I - Introduction to VHDL
1h0'
-
12:00 - 13:00
Synthesis II - Introduction to VHDL
-
12:00
Synthesis II - Introduction to VHDL
1h0'
Speaker: Nizar Abdallah
-
12:00
Synthesis II - Introduction to VHDL
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
(LiberoTM IDE) Design Entry
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15:00
(LiberoTM IDE) Design Entry
1h0'
Speaker: Nizar Abdallah
-
15:00
(LiberoTM IDE) Design Entry
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 17:30
Digital Design I (combinatorial elements)
-
16:30
Digital Design I (combinatorial elements)
1h0'
Speaker: Pirouz Bazargan-Sabet
-
16:30
Digital Design I (combinatorial elements)
1h0'
-
17:30 - 19:00
Digital Design II (sequential elements, Mealy and Moore FSM)
-
17:30
Digital Design II (sequential elements, Mealy and Moore FSM)
1h30'
Speaker: Pirouz Bazargan-Sabat
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17:30
Digital Design II (sequential elements, Mealy and Moore FSM)
1h30'
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20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Introduction to ACETEL Products. Libero IDE Overview and Design flow
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-
09:30 - 10:30
(LiberoTM IDE) Functional Simulation. Synthesis
-
09:30
(LiberoTM IDE) Functional Simulation. Synthesis
1h0'
Speaker: Nizar Abdallah
-
09:30
(LiberoTM IDE) Functional Simulation. Synthesis
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Synthesis III - Advanced VHDL
-
11:00
Synthesis III - Advanced VHDL
1h0'
Speaker: Nizar Abdallah
-
11:00
Synthesis III - Advanced VHDL
1h0'
-
12:00 - 13:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
-
12:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
1h0'
Speaker: Pirouz Bazargan-Sabat
-
12:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. VHDL Simulation Environment. A design example
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15:00
Laboratory Session. VHDL Simulation Environment. A design example
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. VHDL Simulation Environment. A design example
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. VHDL Simulation Environment. A design example. Contd.
-
16:30
Laboratory Session. VHDL Simulation Environment. A design example. Contd.
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. VHDL Simulation Environment. A design example. Contd.
2h30'
-
19:00 - 21:00
Dinner
- 19:00 Dinner 2h0'
-
09:30 - 10:30
(LiberoTM IDE) Functional Simulation. Synthesis
-
-
09:30 - 10:30
(LiberoTM IDE) Place & Route
-
09:30
(LiberoTM IDE) Place & Route
1h0'
Speaker: Nizar Abdallah
-
09:30
(LiberoTM IDE) Place & Route
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Digital arithmetic I (number representations)
-
11:00
Digital arithmetic I (number representations)
1h0'
Speaker: Pirouz Bazargan-Sabet
-
11:00
Digital arithmetic I (number representations)
1h0'
-
12:00 - 13:00
Digital arithmetic II (basic arithmetic operations)
-
12:00
Digital arithmetic II (basic arithmetic operations)
1h0'
Speaker: Pirouz Bazargan-Sabat
-
12:00
Digital arithmetic II (basic arithmetic operations)
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
-
15:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
-
16:30
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
2h30'
-
20:00 - 20:00
Dinner
- 20:00 Dinner
-
09:30 - 10:30
(LiberoTM IDE) Place & Route
-
-
09:30 - 10:30
Design Verification and Timing Concepts
-
09:30
Design Verification and Timing Concepts
1h0'
Speaker: Nizar Abdallah
-
09:30
Design Verification and Timing Concepts
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
(LiberoTM IDE) Timing Constraints and Analysis
-
11:00
(LiberoTM IDE) Timing Constraints and Analysis
1h0'
Speaker: Nizar Abdallah
-
11:00
(LiberoTM IDE) Timing Constraints and Analysis
1h0'
-
12:00 - 13:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
-
12:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
1h0'
Speaker: Maria Liz Crespo
-
12:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
-
15:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:30
Laboratory Session. Finite State Machine: VHDL Description and Simulation
-
16:30
Laboratory Session. Finite State Machine: VHDL Description and Simulation
3h0'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. Finite State Machine: VHDL Description and Simulation
3h0'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Design Verification and Timing Concepts
-
-
09:30 - 10:30
Programmable logic & FPGA architectures
-
09:30
Programmable logic & FPGA architectures
1h0'
Speaker: Nizar Abdallah
-
09:30
Programmable logic & FPGA architectures
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
(LiberoTM IDE) Post-Layout Simulation. Programming
-
11:00
(LiberoTM IDE) Post-Layout Simulation. Programming
1h0'
Speaker: Nizar Abdallah
-
11:00
(LiberoTM IDE) Post-Layout Simulation. Programming
1h0'
-
12:00 - 13:00
Microelectronics at CERN
-
12:00
Microelectronics at CERN
1h0'
Speaker: Paulo Moreira Material: 
lecture notes
-
12:00
Microelectronics at CERN
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Introduction to CMOS technology and VLSI design
-
15:00
Introduction to CMOS technology and VLSI design
1h0'
Speaker: Paulo Moreira
-
15:00
Introduction to CMOS technology and VLSI design
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 17:30
CMOS Technology I
-
16:30
CMOS Technology I
1h0'
Speaker: Paulo Moreira
-
16:30
CMOS Technology I
1h0'
-
17:30 - 19:00
Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
-
17:30
Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
1h30'
Speaker: Maria Liz Crespo
-
17:30
Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
1h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Programmable logic & FPGA architectures
-
-
09:30 - 10:30
Actel Flash FPGA architecture
-
09:30
Actel Flash FPGA architecture
1h0'
Speaker: Nizar Abdallah
-
09:30
Actel Flash FPGA architecture
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
System-on-Chip concepts
-
11:00
System-on-Chip concepts
1h0'
Speaker: Nizar Abdallah
-
11:00
System-on-Chip concepts
1h0'
-
12:00 - 13:00
CMOS Technology II
-
12:00
CMOS Technology II
1h0'
Speaker: Paulo Moreira
-
12:00
CMOS Technology II
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
VLSI Design I
-
15:00
VLSI Design I
1h0'
Speaker: Paulo Moreira
-
15:00
VLSI Design I
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 17:30
Advance FPGA Applications
-
16:30
Advance FPGA Applications
1h0'
Speaker: Alexander Kluge Material:
lecture notes
-
16:30
Advance FPGA Applications
1h0'
-
17:30 - 20:00
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
-
17:30
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
2h30'
Speaker: Carlos Sosa Paez
-
17:30
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Actel Flash FPGA architecture
-
-
09:30 - 10:30
DEMO Actel Fusion Evaluation Board
-
09:30
DEMO Actel Fusion Evaluation Board
1h0'
Speaker: Nizar Abdallah
-
09:30
DEMO Actel Fusion Evaluation Board
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
VLSI design II
-
11:00
VLSI design II
1h0'
Speaker: Paulo Moreira
-
11:00
VLSI design II
1h0'
-
12:00 - 13:00
Advance FPGA applications. A case study in HEP experiments
-
12:00
Advance FPGA applications. A case study in HEP experiments
1h0'
Speaker: Alexander Kluge
-
12:00
Advance FPGA applications. A case study in HEP experiments
1h0'
-
13:00 - 15:00
Break
- 13:00 Break 2h0'
-
15:00 - 16:00
Advance FPGA applications. A case study in HEP experiments (contd)
-
15:00
Advance FPGA applications. A case study in HEP experiments (contd)
1h0'
Speaker: Alexander Kluge
-
15:00
Advance FPGA applications. A case study in HEP experiments (contd)
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
-
16:30
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
2h30'
Speaker: Carlos Sosa Paez
-
16:30
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
DEMO Actel Fusion Evaluation Board
-
-
09:30 - 10:30
Introduction to Fourier Theory
-
09:30
Introduction to Fourier Theory
1h0'
Speaker: Marcelo Magnasco
-
09:30
Introduction to Fourier Theory
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Fourier Theory I
-
11:00
Fourier Theory I
1h0'
Speaker: Marcelo Magnasco
-
11:00
Fourier Theory I
1h0'
-
12:00 - 13:00
Fourier Theory II
-
12:00
Fourier Theory II
1h0'
Speaker: Marcelo Magnasco
-
12:00
Fourier Theory II
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
-
15:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
-
16:30
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Introduction to Fourier Theory
-
-
09:30 - 10:30
Introduction to Digital Signal Processing
-
09:30
Introduction to Digital Signal Processing
1h0'
Speaker: Marcelo Magnasco
-
09:30
Introduction to Digital Signal Processing
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 13:00
Digital Signal Processing I
-
11:00
Digital Signal Processing I
2h0'
Speaker: Marcelo Magnasco
-
11:00
Digital Signal Processing I
2h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
-
15:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
-
16:30
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Introduction to Digital Signal Processing
-
-
09:30 - 10:30
Selected topics on Logic Synthesis and FPGA Debugging
-
09:30
Selected topics on Logic Synthesis and FPGA Debugging
1h0'
Speaker: Andres Cicuttin
-
09:30
Selected topics on Logic Synthesis and FPGA Debugging
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
-
11:00
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
1h0'
Speaker: Andres Cicuttin
-
11:00
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
1h0'
-
12:00 - 13:00
Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
-
12:00
Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
1h0'
Speaker: Maria Liz Crespo
-
12:00
Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
-
15:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
-
16:30
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Selected topics on Logic Synthesis and FPGA Debugging
-
-
09:30 - 10:30
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
-
09:30
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
1h0'
Speaker: Khan Javed Iqbal
-
09:30
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
-
11:00
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
1h0'
Speaker: Khan Javed iqbal
-
11:00
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
1h0'
-
12:00 - 13:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
-
12:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
1h0'
Speaker: Andres Cicuttin
-
12:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
-
15:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
1h0'
Speaker: Andres Cicuttin
-
15:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
-
16:30
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
2h30'
Speaker: Miguel Risco Castillo
-
16:30
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
-
-
09:30 - 10:30
Introduction to two-dimensional digital signal processing.
-
09:30
Introduction to two-dimensional digital signal processing.
1h0'
Speaker: Fabio Mammano
-
09:30
Introduction to two-dimensional digital signal processing.
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Two-dimensional digital signal processing I.
-
11:00
Two-dimensional digital signal processing I.
1h0'
Speaker: Fabio Mammano
-
11:00
Two-dimensional digital signal processing I.
1h0'
-
12:00 - 13:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
-
12:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
1h0'
Speaker: Miguel Risco Castillo
-
12:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. RVI Architecture. Integration of new blocks
-
15:00
Laboratory Session. RVI Architecture. Integration of new blocks
1h0'
Speaker: Miguel Risco Castillo
-
15:00
Laboratory Session. RVI Architecture. Integration of new blocks
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
-
16:30
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
2h30'
Speaker: Miguel Risco Castillo
-
16:30
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
2h30'
-
20:00 - 20:00
Dinner
- 20:00 Dinner
-
09:30 - 10:30
Introduction to two-dimensional digital signal processing.
-
-
09:30 - 10:30
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
-
09:30
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
1h0'
Speaker: Fabio Mammano
-
09:30
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
-
11:00
Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
1h0'
Speaker: Fabio Mammano
-
11:00
Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
1h0'
-
12:00 - 13:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
-
12:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
1h0'
Speaker: Maria Liz Crespo
-
12:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
-
15:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
-
16:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
-
-
09:30 - 10:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
-
09:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
Speaker: Maria Liz Crespo
-
09:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 13:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
-
11:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
2h0'
Speaker: Maria Liz Crespo
-
11:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
2h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
-
15:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
Speaker: Maria Liz Crespo
-
15:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 19:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
-
16:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
2h30'
Speaker: Maria Liz Crespo
-
16:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
2h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
-
-
09:30 - 11:00
System Design: Is Hardware Becoming Software?
-
09:30
System Design: Is Hardware Becoming Software?
1h30'
Speaker: Chris Oh
-
09:30
System Design: Is Hardware Becoming Software?
1h30'
-
11:00 - 11:30
Break
- 11:00 Break 30'
-
11:30 - 13:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
-
11:30
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h30'
Speaker: King Keong Wong, Thiam Sin Lai
-
11:30
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h30'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
-
15:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h0'
Speaker: King Keong Wang, Thiam Sin Lai
-
15:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 18:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
-
16:30
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h30'
Speaker: King Keong Wang, Thiam Sin Lai
-
16:30
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
1h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 11:00
System Design: Is Hardware Becoming Software?
-
-
09:30 - 11:00
Formal Verification Techniques for FPGA
-
09:30
Formal Verification Techniques for FPGA
1h30'
Speaker: Elisha Lye
-
09:30
Formal Verification Techniques for FPGA
1h30'
-
11:00 - 11:30
-
- 11:00 - 30'
-
11:30 - 13:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
-
11:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
Speaker: . Jimmy Yeap
-
11:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
-
15:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
Speaker: Jimmy Yeap
-
15:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
-
16:30 - 17:00
Break
- 16:30 Break 30'
-
17:00 - 18:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
-
17:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
Speaker: Jimmy Yeap
-
17:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
1h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 11:00
Formal Verification Techniques for FPGA
-
-
09:30 - 10:30
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
-
09:30
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
1h0'
Speaker: Weng Fook Lee
-
09:30
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 12:00
An Overview of Microprocessor Architecture & Implementation of a Large Bus Size VLIW Microprocessor on FPGA.
-
11:00
An Overview of Microprocessor Architecture & Implementation of a Large Bus Size VLIW Microprocessor on FPGA.
1h0'
-
11:00
An Overview of Microprocessor Architecture & Implementation of a Large Bus Size VLIW Microprocessor on FPGA.
1h0'
-
12:00 - 13:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
-
12:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h0'
Speaker: Choong Yee Lee
-
12:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
-
15:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h0'
Speaker: Choong Yee Lee
-
15:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 18:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
-
16:30
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h30'
Speaker: Choong Yee Lee
-
16:30
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
1h30'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
-
-
09:30 - 10:30
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
-
09:30
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
1h0'
Speaker: Chew Beng Wah
-
09:30
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
1h0'
-
10:30 - 11:00
Break
- 10:30 Break 30'
-
11:00 - 13:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
-
11:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
2h0'
Speaker: Chew Beng Wah
-
11:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
2h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.
-
15:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.
1h0'
Speaker: Chew Beng Wan
-
15:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 17:30
Challenges in Low Power Design
-
16:30
Challenges in Low Power Design
1h0'
Speaker: Jasmine NG (CADENCE)
-
16:30
Challenges in Low Power Design
1h0'
-
17:30 - 18:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
-
17:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
1h0'
-
17:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
1h0'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
-
-
09:30 - 10:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
-
09:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
1h0'
-
09:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
1h0'
-
10:30 - 11:00
Break proceed to Sport Complex (UA113)
- 10:30 Break proceed to Sport Complex (UA113) 30'
-
11:00 - 13:00
Closing Ceremony (UA113, Sport Complex)
-
11:00
Closing Ceremony (UA113, Sport Complex)
2h0'
-
11:00
Closing Ceremony (UA113, Sport Complex)
2h0'
-
13:00 - 15:00
Lunch
- 13:00 Lunch 2h0'
-
15:00 - 16:00
Certificates of Participation (DK E)
-
15:00
Certificates of Participation (DK E)
1h0'
-
15:00
Certificates of Participation (DK E)
1h0'
-
16:00 - 16:30
Break
- 16:00 Break 30'
-
16:30 - 18:30
Open Discussion
-
16:30
Open Discussion
2h0'
-
16:30
Open Discussion
2h0'
-
20:00 - 22:00
Dinner
- 20:00 Dinner 2h0'
-
09:30 - 10:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design