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VERSION:2.0
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SUMMARY:Digital Signal Processing with FPGA. A Design Example using the µ
 Lab Virtual Panel (constant multiplier and level shifter) (contd).
DTSTART;VALUE=DATE-TIME:20100331T093000Z
DTEND;VALUE=DATE-TIME:20100331T103000Z
DTSTAMP;VALUE=DATE-TIME:20240229T181111Z
UID:indico-contribution-112-0-76@ictp.it
DESCRIPTION:Speakers: \n//indico.ictp.it/event/a09180/session/112/contribu
 tion/76
LOCATION:Mar del Plata - Argentina
URL://indico.ictp.it/event/a09180/session/112/contribution/76
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