BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//CERN//INDICO//EN
BEGIN:VEVENT
SUMMARY:Sequential Logic Described in VHDL - A Design Example
DTSTART;VALUE=DATE-TIME:20121130T122500Z
DTEND;VALUE=DATE-TIME:20121130T132500Z
DTSTAMP;VALUE=DATE-TIME:20260516T051604Z
UID:indico-contribution-77-0-47@ictp.it
DESCRIPTION:Speakers: RAUL ARTECHE DIAZ (CEADEN\, Cuba)\n//indico.ictp.it/
 event/a11204/session/77/contribution/47
LOCATION:Havana - Cuba - Room alternative: Conference Hall
URL://indico.ictp.it/event/a11204/session/77/contribution/47
END:VEVENT
END:VCALENDAR