Scientific Calendar Event



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  • Monday, 19 November 2012
    • 08:30 - 10:30 REGISTRATION
      Location: - Room alternative: Salon de Protocol - CEADEN Theatre
      • 08:30 REGISTRATION 2h0'
        Speaker: ICTP Secretariat
    • 10:30 - 11:00 Coffee Break
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 OPENING CEREMONY
      Location: - Room alternative: CEADEN Theatre
      • 11:00 OPENING CEREMONY 1h0'
    • 12:00 - 13:00 Digital Design
      • 12:00 Digital Design 1h0'
        Speaker: Pirouz BAZARGAN-SABET (Unviersity Pierre & Marie Curie, Paris, France)
        Material: lecture notes
    • 13:00 - 14:30 Lunch Break
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 Digital Design - Combinatorial elements
      • 14:30 Digital Design - Combinatorial elements 1h0'
        Speaker: Pirouz BAZARGAN-SABET
        Material: lecture notes
    • 15:30 - 16:00 Coffee Break
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 FPGA Technology
      • 16:00 FPGA Technology 2h0'
        Speaker: Cristian SISTERNA (University of San Juan, Argentina)
        Material: lecture notes
  • Tuesday, 20 November 2012
    • 09:30 - 10:30 FPGA Design Techniques
      • 09:30 FPGA Design Techniques 1h0'
        Speaker: Cristian SISTERNA
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 FPGA Timing and Tools for High Performance
      • 11:00 FPGA Timing and Tools for High Performance 1h0'
        Speaker: Cristian SISTERNA
    • 12:00 - 13:00 Digital Design - Sequential elements, Mealy and Moore FSM
      • 12:00 Digital Design - Sequential elements, Mealy and Moore FSM 1h0'
        Speaker: Pirouz BAZARGAN-SABET
        Material: lecture notes
    • 13:00 - 14:30 Lunch Break
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 Digital Design - More complex elements: RAM, ROM, buses, pipeline concept, etc
      • 14:30 Digital Design - More complex elements: RAM, ROM, buses, pipeline concept, etc 1h0'
        Speaker: Pirouz BAZARGAN-SABET
        Material: lecture notes
    • 15:30 - 16:00 Coffee Break
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 VHDL for FPGA Design
      • 16:00 VHDL for FPGA Design 2h0'
        Speaker: Cristian SISTERNA
        Material: lecture notes
  • Wednesday, 21 November 2012
    • 09:30 - 10:30 VHDL for FPGA Design 2
      • 09:30 VHDL for FPGA Design 2 1h0'
        Speaker: Cristian SISTERNA
    • 10:30 - 11:00 Coffee Break
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 VHDL for FPGA Design 3
      • 11:00 VHDL for FPGA Design 3 1h0'
        Speaker: Cristian SISTERNA
    • 12:00 - 13:00 Digital arithmetic - Number representations
      • 12:00 Digital arithmetic - Number representations 1h0'
        Speaker: Pirouz BAZARGAN-SABET
        Material: lecture notes
    • 13:00 - 14:30 Lunch Break
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 Digital arithmetic - Basic arithmetic operations
      • 14:30 Digital arithmetic - Basic arithmetic operations 1h0'
        Speaker: Pirouz BAZARGAN-SABET
        Material: lecture notes
    • 15:30 - 16:00 Coffee Break
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 VHDL for FPGA Design 4
      • 16:00 VHDL for FPGA Design 4 2h0'
        Speaker: Cristian SISTERNA
  • Thursday, 22 November 2012
    • 09:30 - 10:30 VHDL for FPGA Design 5
      • 09:30 VHDL for FPGA Design 5 1h0'
        Speaker: Cristian SISTERNA
    • 10:30 - 11:00 Coffee Break
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 VHDL for FPGA Design 6
      • 11:00 VHDL for FPGA Design 6 1h0'
        Speaker: Cristian SISTERNA
    • 12:00 - 13:00 Advanced Scientific Applications of FPGA
      • 12:00 Advanced Scientific Applications of FPGA 1h0'
        Speaker: Alexander KLUGE (CERN, Geneva, Switzerland)
        Material: Movies lecture notes
    • 13:00 - 14:30 Lunch Break
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 Advanced Scientific Applications of FPGA 2
      • 14:30 Advanced Scientific Applications of FPGA 2 1h0'
        Speaker: Alexander KLUGE
        Material: lecture notes
    • 15:30 - 16:00 Coffee Break
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 FPGA Debugging
      • 16:00 FPGA Debugging 2h0'
        Speaker: Andres CICUTTIN (ICTP, Trieste, Italy)
        Material: lecture notes
  • Friday, 23 November 2012
    • 09:30 - 10:30 Advanced Scientific Applications of FPGA 3
      • 09:30 Advanced Scientific Applications of FPGA 3 1h0'
        Speaker: Alexander KLUGE
        Material: lecture notes
    • 10:30 - 11:00 Coffee Break
      • 10:30 Coffee Break 30'
    • 11:00 - 12:00 Advanced Scientific Applications of FPGA 4
      • 11:00 Advanced Scientific Applications of FPGA 4 1h0'
        Speaker: Alexander KLUGE
    • 12:00 - 13:00 Wishbone IP Interface Standard
      • 12:00 Wishbone IP Interface Standard 1h0'
        Speaker: Andres CICUTTIN
        Material: lecture notes
    • 13:00 - 14:30 Lunch Break
      • 13:00 Lunch Break 1h30'
    • 14:30 - 15:30 Wishbone IP Interface Standard 2
      • 14:30 Wishbone IP Interface Standard 2 1h0'
        Speaker: Andres CICUTTIN
        Material: Manual
    • 15:30 - 16:00 Coffee Break
      • 15:30 Coffee Break 30'
    • 16:00 - 18:00 VHDL for FPGA Design 7
      • 16:00 VHDL for FPGA Design 7 2h0'
        Speaker: Cristian SISTERNA
    • 18:00 - 20:30 Welcome Dinner
      “Manantial” Restaurant in Le Select Complex
      • 18:00 Welcome Dinner 2h30'
  • Monday, 26 November 2012
    • 08:30 - 09:30 Digital Signal Processing
      • 08:30 Digital Signal Processing 1h0'
        Speaker: Diego COSTA (University of San Luis, Argentina)
        Material: lecture notes
    • 09:30 - 10:00 Coffee Break
      • 09:30 Coffee Break 30'
    • 10:00 - 11:00 Digital Signal Processing 2
      • 10:00 Digital Signal Processing 2 1h0'
        Speaker: Diego COSTA
        Material: lecture notes
    • 11:00 - 12:00 Advanced Topics in Digital Signal Processing
      • 11:00 Advanced Topics in Digital Signal Processing 1h0'
        Speaker: Marcelo MAGNASCO (Rockfeller Uinveristy, NYC, USA)
        Material: lecture notes
    • 12:00 - 13:30 Lunch Break
      • 12:00 Lunch Break 1h30'
    • 13:30 - 14:30 Advanced Topics in Digital Signal Processing2
      • 13:30 Advanced Topics in Digital Signal Processing2 1h0'
        Speaker: Marcelo MAGNASCO
        Material: lecture notes
    • 14:30 - 15:00 Coffee Break
      • 14:30 Coffee Break 30'
    • 16:00 - 18:00 Digital Signal Processing 3
      • 16:00 Digital Signal Processing 3 2h0'
        Speaker: Diego COSTA
        Material: lecture notes
  • Tuesday, 27 November 2012
    • 08:30 - 09:30 Microelectronics at CERN
      • 08:30 Microelectronics at CERN 1h0'
        Speaker: Paulo MOREIRA (CERN, Geneva, Switzerland)
        Material: lecture notes
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 10:55 Introduction to CMOS technology and VLSI Design
      • 09:55 Introduction to CMOS technology and VLSI Design 1h0'
        Speaker: Paulo MOREIRA
    • 10:55 - 11:55 Applications in Digital Signal Processing
      • 10:55 Applications in Digital Signal Processing 1h0'
        Speaker: Marcelo MAGNASCO
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Applications in Digital Signal Processing 2
      • 13:25 Applications in Digital Signal Processing 2 1h0'
        Speaker: Marcelo MAGNASCO
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Digital Signal Processing 4
      • 14:50 Digital Signal Processing 4 2h0'
        Speaker: Diego COSTA
        Material: lecture notes
  • Wednesday, 28 November 2012
    • 08:30 - 09:30 CMOS technology
      • 08:30 CMOS technology 1h0'
        Speaker: Paulo MOREIRA
        Material: lecture notes
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 10:55 VLSI Design
      • 09:55 VLSI Design 1h0'
        Speaker: Paulo MOREIRA
    • 10:55 - 11:55 Digital Signal Processing 5
      • 10:55 Digital Signal Processing 5 1h0'
        Speaker: Diego COSTA
        Material: lecture notes
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Digital Signal Processing 6
      • 13:25 Digital Signal Processing 6 1h0'
        Speaker: Diego COSTA
        Material: lecture notes
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 15:50 Multidisciplinary Laboratory at ICTP
      Location: - Room alternative: Conference Hall
      • 14:50 Multidisciplinary Laboratory at ICTP 1h0'
        Speaker: Maria Liz CRESPO (ICTP, Trieste, Italy)
        Material: lecture notes
    • 15:50 - 16:50 ISE WebPACK Design Software - Testbench - A Design Example
      Location: - Room alternative: Conference Hall
      • 15:50 ISE WebPACK Design Software - Testbench - A Design Example 1h0'
        Speaker: Cristian SISTERNA
        Material: Tutorial
  • Thursday, 29 November 2012
    • 08:30 - 09:30 Laboratory Overview
      • 08:30 Laboratory Overview 1h0'
        Speaker: Maria Liz CRESPO
        Material: Exercises
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Combinational Logic Described in VHDL - Description, Synthesis and Simulation
      • 09:55 Combinational Logic Described in VHDL - Description, Synthesis and Simulation 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Hardware Description of FPGA Development Platform: Nexys 2
      Location: - Room alternative: Conference Hall
      • 13:25 Hardware Description of FPGA Development Platform: Nexys 2 1h0'
        Speaker: Miguel RISCO CASTILLO (Technological University of Peru, Lima , Peru)
    • 14:25 - 14:50 Coffee Break
      Location: - Room alternative: near Laboratory area
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Combinational Logic Described in VHDL - Synthesis and Implementation
      • 14:50 Combinational Logic Described in VHDL - Synthesis and Implementation 2h0'
        Speaker: Tutors
  • Friday, 30 November 2012
    • 08:30 - 09:30 Combinational Logic Described in VHDL - Synthesis and Implementation
      • 08:30 Combinational Logic Described in VHDL - Synthesis and Implementation 1h0'
        Speaker: Tutors
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Combinational Logic Described in VHDL - Synthesis and Implementation
      • 09:55 Combinational Logic Described in VHDL - Synthesis and Implementation 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Sequential Logic Described in VHDL - A Design Example
      Location: - Room alternative: Conference Hall
      • 13:25 Sequential Logic Described in VHDL - A Design Example 1h0'
        Speaker: Raul ARTECHE DIAZ (CEADEN, Cuba)
        Material: lecture notes
    • 14:25 - 14:50 Coffee Break
      Location: - Room alternative: near Laboratory area
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Sequential Logic Described in VHDL
      • 14:50 Sequential Logic Described in VHDL 2h0'
        Speaker: Tutors
  • Monday, 3 December 2012
    • 08:30 - 09:30 Sequential Logic Described in VHDL
      • 08:30 Sequential Logic Described in VHDL 1h0'
        Speaker: Tutors
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Sequential Logic Described in VHDL
      • 09:55 Sequential Logic Described in VHDL 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Sequential Logic Described in VHDL
      • 13:25 Sequential Logic Described in VHDL 1h0'
        Speaker: Tutors
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Sequential Logic Described in VHDL
      • 14:50 Sequential Logic Described in VHDL 2h0'
        Speaker: Tutors
  • Tuesday, 4 December 2012
    • 08:30 - 09:30 Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example.
      Location: - Room alternative: Conference Hall
      • 08:30 Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example. 1h0'
        Speaker: Carlos SOSA PAEZ (University of San Luis, Argentina)
        Material: lecture notes
    • 09:30 - 09:55 Coffee Break
      Location: - Room alternative: near Laboratory area
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Digital Signal Processing with FPGA
      • 09:55 Digital Signal Processing with FPGA 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Digital Signal Processing with FPGA
      • 13:25 Digital Signal Processing with FPGA 1h0'
        Speaker: Tutors
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Digital Signal Processing with FPGA
      • 14:50 Digital Signal Processing with FPGA 2h0'
        Speaker: Tutors
  • Wednesday, 5 December 2012
    • 08:30 - 09:30 Digital Signal Processing with FPGA
      • 08:30 Digital Signal Processing with FPGA 1h0'
        Speaker: Tutors
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Digital Signal Processing with FPGA
      • 09:55 Digital Signal Processing with FPGA 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Digital Signal Processing with FPGA
      • 13:25 Digital Signal Processing with FPGA 1h0'
        Speaker: Tutors
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Digital Signal Processing with FPGA
      • 14:50 Digital Signal Processing with FPGA 2h0'
        Speaker: Tutors
  • Thursday, 6 December 2012
    • 08:30 - 09:30 Digital Signal Processing with FPGA
      • 08:30 Digital Signal Processing with FPGA 1h0'
        Speaker: Tutors
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Digital Signal Processing with FPGA
      • 09:55 Digital Signal Processing with FPGA 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Reconfigurable Virtual Instrumentation (RVI) based on FPGA
      Location: - Room alternative: Conference Hall
      • 13:25 Reconfigurable Virtual Instrumentation (RVI) based on FPGA 1h0'
        Speaker: Maria Liz Crespo
        Material: lecture notes
    • 14:25 - 14:50 Coffee Break
      Location: - Room alternative: near Conference Hall
      • 14:25 Coffee Break 25'
    • 14:50 - 15:50 ICTP RVI platform - Demo
      Location: - Room alternative: Conference Hall
      • 14:50 ICTP RVI platform - Demo 1h0'
        Speaker: Miguel RISCO CASTILLO
    • 15:50 - 16:50 Distribution of Certificates of Attendance
      Location: - Room alternative: Conference Hall
      • 15:50 Distribution of Certificates of Attendance 1h0'
    • 18:00 - 20:00 Farewell Party
      venue tbc
      • 18:00 Farewell Party 2h0'
  • Friday, 7 December 2012
    • 08:30 - 09:30 Projects on RVI and DSP
      • 08:30 Projects on RVI and DSP 1h0'
        Speaker: Tutors
    • 09:30 - 09:55 Coffee Break
      • 09:30 Coffee Break 25'
    • 09:55 - 11:55 Projects on RVI and DSP
      • 09:55 Projects on RVI and DSP 2h0'
        Speaker: Tutors
    • 11:55 - 13:25 Lunch Break
      • 11:55 Lunch Break 1h30'
    • 13:25 - 14:25 Projects on RVI and DSP
      • 13:25 Projects on RVI and DSP 1h0'
        Speaker: Tutors
    • 14:25 - 14:50 Coffee Break
      • 14:25 Coffee Break 25'
    • 14:50 - 16:50 Projects on RVI and DSP
      • 14:50 Projects on RVI and DSP 2h0'
        Speaker: Tutors