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International Training Workshop on FPGA Design for Scientific Instrumentation and Computing | (smr 2499)
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  • Monday, 11 November 2013
    • 08:00 - 10:00 REGISTRATION AND ADMINISTRATIVE FORMALITIES 
      After you have Registered: Administrative Formalities (daily living allowances/travel reimbursements, bank transactions, etc.) at the E. Fermi Building - just above the Leonardo Da Vinci Bldg. 
- Meal coupons: balance will be issued by the Guesthouse Receptions one day after the on-line registration is completed according to the following timetables: 
GALILEO Guesthouse: Tuesday to Friday 10.00-12.00 & 13.00-15.00 
ADRIATICO Guesthouse: Tuesday To Friday 13.00-15.00 


PLEASE NOTE: There will be extra shuttle bus services to and from the ICTP buildings ONLY on the first day of the activity. Please see attached time schedule.

***

Late arrivals:  Secretariat Office No. 1 (Adriatico Guest House Lower Level)
      Location:
    • 10:00 - 10:30 OPENING and WELCOME
      Location:
      • 10:00 OPENING and WELCOME 30'
        Speaker: Andres CICUTTIN, Maria Liz CRESPO, Julio DONDO GAZZANO
    • 10:30 - 11:30 FPGA Technology
      Location:
      • 10:30 FPGA Technology 1h0'
        Speaker: Cristian SISTERNA (University of San Juan, San Juan, Argentina)
        Material: lecture notes
    • 11:30 - 12:30 FPGA Design Techniques
      Location:
      • 11:30 FPGA Design Techniques 1h0'
        Speaker: Cristian SISTERNA
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Digital Design - Combinatorial elements
      Location:
      • 14:00 Digital Design - Combinatorial elements 1h0'
        Speaker: Pirouz BAZARGAN-SABET (Unviersity Pierre & Marie Curie, Paris, France)
        Material: lecture notes
    • 15:00 - 16:00 Digital Design - Sequential elements, Mealy and Moore FSM
      Location:
      • 15:00 Digital Design - Sequential elements, Mealy and Moore FSM 1h0'
        Speaker: Pirouz BAZARGAN-SABET
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 17:30 FPGA Timing and Tools for High Performance
      Location:
      • 16:30 FPGA Timing and Tools for High Performance 1h0'
        Speaker: Cristian SISTERNA
    • 17:30 - 18:30 VHDL for FPGA Design
      Location:
      • 17:30 VHDL for FPGA Design 1h0'
        Speaker: Cristian SISTERNA
  • Tuesday, 12 November 2013
    • 09:00 - 10:00 Digital Design - More complex elements: RAM, ROM, buses, pipeline concept
      Location:
      • 09:00 Digital Design - More complex elements: RAM, ROM, buses, pipeline concept 1h0'
        Speaker: Pirouz BAZARGAN-SABET
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 11:30 Digital signals and systems
      Location:
      • 10:30 Digital signals and systems 1h0'
        Speaker: Massimiliano NOLICH (Università degli Studi di Trieste, Trieste, Italy)
    • 11:30 - 12:30 Digital processing of analog signals
      Location:
      • 11:30 Digital processing of analog signals 1h0'
        Speaker: Massimiliano NOLICH
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 VHDL for FPGA Design (cont.)
      Location:
      • 14:00 VHDL for FPGA Design (cont.) 1h0'
        Speaker: Cristian SISTERNA
    • 15:00 - 16:00 Discrete Fourier Transform
      Location:
      • 15:00 Discrete Fourier Transform 1h0'
        Speaker: Massimiliano NOLICH
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 17:30 Digital arithmetic - Number representations
      Location:
      • 16:30 Digital arithmetic - Number representations 1h0'
        Speaker: Pirouz BAZARGAN-SABET
    • 17:30 - 19:00 Digital arithmetic - Arithmetic operations
      Location:
      • 17:30 Digital arithmetic - Arithmetic operations 1h30'
        Speaker: Pirouz BAZARGAN-SABET
  • Wednesday, 13 November 2013
    • 09:00 - 10:00 High Level Synthesis: how to improve FPGA design productivity
      Location:
      • 09:00 High Level Synthesis: how to improve FPGA design productivity 1h0'
        Speaker: Fernando RINCON CALLE (Universty of Castilla-La Mancha, Spain)
        Material: lecture notes
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 11:30 FPGA Debugging
      Location:
      • 10:30 FPGA Debugging 1h0'
        Speaker: Andres CICUTTIN (ICTP, Trieste, Italy)
    • 11:30 - 12:30 VHDL for FPGA Design (contd.)
      Location: Adriatico Guest House Giambiagi Lecture Hall
      • 11:30 VHDL for FPGA Design (contd.) 1h0'
        Speaker: Cristian SISTERNA
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 16:00 VHDL for FPGA Design (contd.)
      Location:
      • 14:00 VHDL for FPGA Design (contd.) 2h0'
        Speaker: Cristian SISTERNA
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 17:00 Overview of Lab Sessions
      Location: Adriatico Guest House Informatics Lab.
      • 16:30 Overview of Lab Sessions 30'
        Speaker: Maria Liz CRESPO (ICTP, Trieste, Italy)
        Material: Exercise
    • 17:00 - 17:30 ISE WebPACK Design Software - Testbench - A Design Example
      Location:
      • 17:00 ISE WebPACK Design Software - Testbench - A Design Example 30'
        Speaker: Cristian SISTERNA
    • 17:30 - 19:00 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
      Location:
      • 17:30 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation 1h30'
        Speaker: Krishna M. KHARE, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Thursday, 14 November 2013
    • 09:00 - 10:00 Microelectronics at CERN - Introduction to CMOS technology and VLSI Design
      Location:
      • 09:00 Microelectronics at CERN - Introduction to CMOS technology and VLSI Design 1h0'
        Speaker: Sandro BONACINI (CERN, Geneva, Switzerland)
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 11:30 CMOS technology
      Location:
      • 10:30 CMOS technology 1h0'
        Speaker: Sandro BONACINI
        Material: lecture notes
    • 11:30 - 12:30 A primer on custom-precision floating-point arithmetic
      Location:
      • 11:30 A primer on custom-precision floating-point arithmetic 1h0'
        Speaker: Manfred MUECKE (Sustainable Computing Research, Vienna, Austria)
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Automated design of ASIP and accelerator based sub-systems for high-performance applications
      Location:
      • 14:00 Automated design of ASIP and accelerator based sub-systems for high-performance applications 1h0'
        Speaker: Lech JOZWIAK (Eindhoven University of Technology, Eindhoven, The Netherlands)
    • 15:00 - 15:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 15:00 Coffee Break 30'
    • 15:30 - 18:30 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
      Location:
      • 15:30 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation 3h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 19:00 - 21:00 Reception
      Location: Adriatico Guest House Cafeteria
      • 19:00 Reception 2h0'
  • Friday, 15 November 2013
    • 09:00 - 10:00 VLSI Design
      Location:
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 11:30 Evolution of Multicore Architectures: design strategies, languages and tools
      Location:
      • 10:30 Evolution of Multicore Architectures: design strategies, languages and tools 1h0'
        Speaker: Carlos VALDERRAMA (Polytechnique of Mons, Mons, Belgium)
    • 11:30 - 12:30 Digital filter design
      Location:
      • 11:30 Digital filter design 1h0'
        Speaker: Massimiliano NOLICH
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Filter design examples
      Location:
      • 14:00 Filter design examples 1h0'
        Speaker: Massimiliano NOLICH
    • 15:00 - 15:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 15:00 Coffee Break 30'
    • 15:30 - 16:30 VLSI Design (contd.)
      Location: Adriatico Guest House Giambiagi Lecture Hall
      • 15:30 VLSI Design (contd.) 1h0'
        Speaker: Sandro BONACINI
    • 16:30 - 18:30 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
      Location:
      • 16:30 Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation 2h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Monday, 18 November 2013
    • 09:00 - 10:00 Introduction to SoC Modeling
      Location:
      • 09:00 Introduction to SoC Modeling 1h0'
        Speaker: Julio DONDO GAZZANO (Universty of Castilla-La Mancha, Spain)
        Material: lecture notes
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 12:30 Advanced SOC-FPGA trends
      Location:
      • 10:30 Advanced SOC-FPGA trends 2h0'
        Speaker: Nizar ABDALLAH (Microsemi, Mountain View, CA, USA)
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Research and Training at the ICTP Multidisciplinary Laboratory (ICTP Mlab)
      Location: Adriatico Guest House Giambiagi Lecture Hall
      • 14:00 Research and Training at the ICTP Multidisciplinary Laboratory (ICTP Mlab) 1h0'
        Speaker: Maria Liz CRESPO
    • 15:00 - 16:00 Hardware Description of FPGA Development Platform
      Location:
      • 15:00 Hardware Description of FPGA Development Platform 1h0'
        Speaker: Miguel RISCO CASTILLO (Technological University of Peru, Lima , Peru)
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 18:30 FPGA Design Implementation
      Location:
      • 16:30 FPGA Design Implementation 2h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Tuesday, 19 November 2013
    • 09:00 - 10:00 Advanced SOC-FPGA trends (cont.)
      Location:
      • 09:00 Advanced SOC-FPGA trends (cont.) 1h0'
        Speaker: Nizar ABDALLAH
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 12:30 Advanced Scientific Applications of FPGA
      Location:
      • 10:30 Advanced Scientific Applications of FPGA 2h0'
        Speaker: Alexander KLUGE (CERN, Geneva, Switzerland)
        Material: lecture notes
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Life at the edge: critical dynamics in the brain
      Location: Leonardo da Vinci Building Main Lecture Hall
      • 14:00 Life at the edge: critical dynamics in the brain 1h0'
        Speaker: Marcelo MAGNASCO (Rockfeller Uinveristy, NYC, USA)
        Material: abstract
    • 15:00 - 15:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 15:00 Coffee Break 30'
    • 15:30 - 18:30 FPGA Design Implementation
      Location:
      • 15:30 FPGA Design Implementation 3h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Wednesday, 20 November 2013
    • 09:00 - 10:00 Advanced Topics in Digital Signal Processing
      Location:
      • 09:00 Advanced Topics in Digital Signal Processing 1h0'
        Speaker: Marcelo MAGNASCO
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 11:30 Wishbone IP Interface Standard
      Location:
      • 10:30 Wishbone IP Interface Standard 1h0'
        Speaker: Andres CICUTTIN
    • 11:30 - 12:30 Advanced Applications of Digital Signal Processing
      Location:
      • 11:30 Advanced Applications of Digital Signal Processing 1h0'
        Speaker: Marcelo MAGNASCO
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 PC-FPGA Serial Communication - Design Example
      Location:
      • 14:00 PC-FPGA Serial Communication - Design Example 1h0'
        Speaker: Thulasiraman NANDHA KUMAR (The University of Nottingham, Malaysia Campus, Selangor, Malaysia)
        Material: lecture notes
    • 15:00 - 16:00 FPGA Design Implementation
      Location:
      • 15:00 FPGA Design Implementation 1h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 17:30 Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example.
      Location:
      • 16:30 Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example. 1h0'
        Speaker: Carlos SOSA PAEZ (University of San Luis, San Luis, Argentina)
    • 17:30 - 18:30 Digital Signal Processing with FPGA
      Location:
      • 17:30 Digital Signal Processing with FPGA 1h0'
        Speaker: Krishna M. KHARE, Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Thursday, 21 November 2013
    • 09:00 - 10:00 Embedded system design for instrumentation using FPGA
      Location:
      • 09:00 Embedded system design for instrumentation using FPGA 1h0'
        Speaker: Krishna Mohan KHARE
        Material: lecture notes
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 12:30 Digital Signal Processing with FPGA
      Location:
      • 10:30 Digital Signal Processing with FPGA 2h0'
        Speaker: Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:30 - 16:30 Research Projects at the ICTP Mlab
      Location:
      • 14:30 Research Projects at the ICTP Mlab 2h0'
    • 16:30 - 17:00 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:30 Coffee Break 30'
    • 17:30 - 19:00 Digital Signal Processing with FPGA
      Location: Adriatico Guest House Informatics Lab.
      • 17:30 Digital Signal Processing with FPGA 1h30'
        Speaker: Thulasiraman NANDHA KUMAR, Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
  • Friday, 22 November 2013
    • 09:00 - 10:00 Digital Signal Processing with FPGA
      Location:
      • 09:00 Digital Signal Processing with FPGA 1h0'
        Speaker: Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 10:00 - 10:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 10:00 Coffee Break 30'
    • 10:30 - 12:30 Digital Signal Processing with FPGA
      Location:
      • 10:30 Digital Signal Processing with FPGA 2h0'
        Speaker: Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 12:30 - 14:00 Lunch Break
      Location:
      • 12:30 Lunch Break 1h30'
    • 14:00 - 15:00 Digital Signal Processing with FPGA
      Location:
      • 14:00 Digital Signal Processing with FPGA 1h0'
        Speaker: Miguel A. RISCO CASTILLO, Cristian A. SISTERNA , Carlos F. SOSA PAEZ
    • 15:00 - 16:00 Distribution of Certificates and Concluding Remarks
      Location: Adriatico Guest House Giambiagi Lecture Hall
      • 15:00 Distribution of Certificates and Concluding Remarks 1h0'
        Speaker: Andres CICUTTIN, Maria Liz CRESPO, Julio D. DONDO GAZZANO
    • 16:00 - 16:30 Coffee Break
      Location: Adriatico Guest House (Lower Level 1)
      • 16:00 Coffee Break 30'
    • 16:30 - 18:30 Final Discussions
      Location: Adriatico Guest House Giambiagi Lecture Hall
      • 16:30 Final Discussions 2h0'
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