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VERSION:2.0
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BEGIN:VEVENT
SUMMARY:Digital Signal Processing with FPGA. A Design Example using the µ
 Lab Virtual Panel (constant multiplier and level shifter).
DTSTART;VALUE=DATE-TIME:20100331T080000Z
DTEND;VALUE=DATE-TIME:20100331T090000Z
DTSTAMP;VALUE=DATE-TIME:20240229T180359Z
UID:indico-contribution-75@ictp.it
DESCRIPTION:Speakers: ANDRES AIRABELLA ()\n//indico.ictp.it/event/a09180/s
 ession/110/contribution/75
LOCATION:Mar del Plata - Argentina
URL://indico.ictp.it/event/a09180/session/110/contribution/75
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