High density integrated circuits (HDICs) are facing challenges in their further development aiming higher device performances. HDICs performances have been improved by shrinking transistor’s dimensions which are now at the nanoscale.
Low dimensions led to device engineering such as the AHLATID, LDD, Large angle Tilt, LATID or drain engineered MOSFETs. ONO MOSFETs are introduced to increase gate dielectric breakdown, which is more pronounced using high k dielectric such as Hafnium oxide HfO2.Besides the engineered MOSFET, SOI (Silicon On Insulator) is an alternative technology to overcome short channel effects (especially hot carriers) in HDICs. SOI devices can be single or double gate, rectangular or surrounded gate. Bulk MOSFETs are featured to include drain halo doping to reduce impact ionization near the drain regions.
New device technologies are introduced in the case of NanoMOSFETs, Ultrathin body MOSFET and ballistic MOSFETs in which electronic transport models are based on ballistic transport are the candidates for the future HDCIs. The CNFET (Carbon Nanotube MOSFET) is another alternative of NanoFETs but not ready at all for the HDICs integration. The same thing is observed in the case of the Molecular Transistor which is under investigation and developments.
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