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Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation

Place

Location: ICTP
Address: Via Grignano, 9 34151 - Trieste (Italy)
Room: Adriatico Guest House (Giambiagi Lecture Hall)
Date: 15 Nov 16:30 - 18:30

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Displaying 1 contribution out of 1
Presented by KRISHNA M. KHARE, THULASIRAMAN NANDHA KUMAR, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ on 15/11/2013 at 16:30
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Organizers

A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo