Description |
The workshop will cover key aspects of fully programmable Systems-on-Chip (SoC) and their applications to scientific instrumentation and reconfigurable computing. SoC is an affordable technology typically used in systems requiring high-parallelism, low-latency, and high-throughput. Modern nuclear and particle physics experiments require online data acquisition (DAQ) systems that process multiple parallel signals coming from detectors and reduce both the data rate and the amount of data to be storage in disk for further offline analysis. These systems usually rely on:
Participants will be familiarized with open-source methods, software design tools, and hardware platforms through tutorials and hands-on activities. They will build embedded instruments using low-cost detectors and SoC-FPGA devices. Topics
Grants: A limited number of grants are available to support the attendance of selected participants, with priority given to participants from developing countries. There is no registration fee. Venue: Qatar University |
Workshop on Fully-Programmable Systems-on-Chip for Scientific Applications | (smr 3983)
Go to day
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08:00 - 17:00
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08:00
Registration formalities
30'
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08:30
Opening Ceremony Remarks
15'
Speaker: Maria Liz CRESPO (ICTP, Italy), Mohammed AL-HITMI (Qatar University), Muhammad Enamul Hoque CHOWDHURY (Qatar University) -
08:45
What is ICTP?
15'
Speaker: Maria Liz CRESPO (ICTP, Italy) Material: Slides -
09:00
Group Picture
10'
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09:10
Workshop Outline
20'
Speaker: Maria Liz CRESPO (ICTP, Italy) Material: Slides -
09:30
System-on-Chip (SoC) and Design Methodology
1h0'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 10:30 Coffee Break 30'
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11:00
Development Board: Zynq SoC
45'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides -
11:45
C for Embedded Systems
45'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 12:30 Lunch Break 1h0'
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13:30
Virtual Machine and User environment
15'
Speaker: Maynor BALLINA (ICTP, Italy) -
13:45
Guide for Lab 1 - Hello World and GPIO In/Out
15'
Speaker: Maynor BALLINA (ICTP, Italy) Material: Slides -
14:00
Lab 1 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 15:30 Tea/Coffee-Break 20'
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15:50
Lab 1 with tutors
1h10'
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08:00
Registration formalities
30'
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08:00 - 17:00
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08:00 - 17:00
- 08:00 Breakfast 30'
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08:30
Custom IP Cores
1h0'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides -
09:30
Digital Pulse Processing for X-ray Photon Detection and Energy Measurement
1h0'
remote
Speaker: Andres CICUTTIN (ICTP, Italy) Material: Lecture Notes - 10:30 Tea/Coffee-Break 30'
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11:00
VHDL for Synthesis
45'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides -
11:45
VHDL for Simulation
45'
Speaker: Cristian SISTERNA (Universidad Nacional de San Juan, Argentina) Material: Slides - 12:30 Lunch Break 1h0'
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13:30
Guide for Lab 2 - ComBlock and RTL instantiation
30'
Speaker: Maynor BALLINA (ICTP, Italy) Material: Slides -
14:00
Lab 2 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 15:30 Tea/Coffee-Break 20'
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15:50
Lab 2 with tutors
1h10'
Speaker: Lecturers and Lab Tutors
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08:00 - 17:00
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08:00 - 17:00
- 08:00 Breakfast 30'
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08:30
High Level Synthesis (HLS)
1h0'
Speaker: Fernando RINCON CALLE (University of Castilla-La Mancha, Spain) Material: Slides -
09:30
HLS Demo
1h0'
Speaker: Fernando RINCON CALLE (University of Castilla-La Mancha, Spain) - 10:30 Tea/Coffee-Break 30'
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11:00
Real Time Operating System (FreeRTOS)
45'
Speaker: Luis Guillermo GARCÍA ORDÓÑEZ (ICTP, Italy) Material: Slides -
11:45
Tool Command Language (TCL)
45'
Speaker: Luis Guillermo GARCÍA ORDÓÑEZ (ICTP, Italy) Material: Slides - 12:30 Lunch Break 1h0'
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13:30
Guide for Lab 3 - SoC-FPGA Development Framework: UDMA & Jupyter Notebook
30'
Speaker: Luis Guillermo GARCÍA ORDÓÑEZ (ICTP, Italy) -
14:00
Lab 3 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 15:30 Tea/Coffee-Break 20'
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15:50
Lab 3 with tutors
1h10'
Speaker: Lecturers and Lab Tutors
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08:00 - 17:00
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08:00 - 11:00
- 08:00 Breakfast 30'
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08:30
FPGA for Accelerating Machine Learning (ML) Algorithms
1h0'
Speaker: Romina MOLINA (ICTP, Italy) Material: Slides -
09:30
Digital Pulse Processing (DPP) for Isotope Identification
1h0'
Speaker: Mladen BOGOVAC (IAEA, Austria) - 10:30 Tea/Coffee-Break 30'
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11:00 - 17:00
Paralell lab session (Lab 2)
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11:00
Pulse acquisition and detector characterization
30'
Speaker: Mladen BOGOVAC (IAEA, Austria) -
11:30
Project 2 with tutors
1h0'
Speaker: Lecturers and Lab Tutors - 12:30 Lunch Break 1h0'
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13:30
DPP for isotope identification
30'
Speaker: Mladen BOGOVAC (IAEA, Austria) -
14:00
Project 2 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 15:30 Tea/Coffee-Break 20'
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15:50
Project 2 with tutors
1h10'
Speaker: Lecturers and Lab Tutors
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11:00
Pulse acquisition and detector characterization
30'
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11:00 - 17:00
Paralell lab session (Lab 1)
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11:00
ML and SoC-FPGA: Training and Compression
30'
Speaker: Romina MOLINA (ICTP, Italy) -
11:30
Project 1 with tutors
1h0'
Speaker: Lecturers and Lab Tutors - 12:30 Lunch Break 1h0'
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13:30
ML and SoC-FPGA: Integration with a hardware design synthesis tool for ML
30'
Speaker: Romina MOLINA (ICTP, Italy) -
14:00
Project 1 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 15:30 Tea/Coffee-Break 20'
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15:50
Project 1 with tutors
1h10'
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11:00
ML and SoC-FPGA: Training and Compression
30'
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19:30 - 21:30
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19:30
Gala Dinner
2h0'
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19:30
Gala Dinner
2h0'
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08:00 - 11:00
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08:00 - 10:00
- 08:00 Breakfast 30'
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08:30
Healthcare system: practical implementation of SoC
45'
Speaker: SAWAL HAMID BIN MD ALI (University Kebangsaan Malaysia) Material: Slides -
09:15
FPGAs and Quantum Computers
45'
Speaker: Agustin SILVA Technology Innovation Institute (TII) Abu Dhabi United Arab Emirates (TII, United Arab Emirates)
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10:00 - 15:50
Paralell lab session (Lab 2)
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10:00
Baseline restorer and pile-up rejection
30'
Speaker: Mladen BOGOVAC (IAEA, Austria) - 10:30 Tea/Coffee-Break 30'
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11:00
Project 2 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 12:30 Lunch Break 1h0'
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13:30
Project 2 with tutors
2h20'
Speaker: Lecturers and Lab Tutors
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10:00
Baseline restorer and pile-up rejection
30'
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10:00 - 17:00
Paralell lab session (Lab 1)
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10:00
ML and SoC-FPGA: Hardware assessment framework
30'
Speaker: Romina MOLINA (ICTP, Italy) - 10:30 Tea/Coffee-Break 30'
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11:00
Project 1 with tutors
1h30'
Speaker: Lecturers and Lab Tutors - 12:30 Lunch Break 1h0'
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13:30
Project 1 with tutors
2h20'
- 15:50 Tea/Coffee-Break 20'
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16:10
ICTP programmes and MLab activities
20'
Speaker: Maria Liz CRESPO (ICTP, Italy) Material: Slides - 16:30 Group Picture 10'
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16:40
Distribution of Certificates and Closing Remarks
20'
Speaker: Maria Liz CRESPO (ICTP, Italy), Mohammed AL-HITMI (Qatar University), Muhammad Enamul Hoque CHOWDHURY (Qatar University), SAWAL HAMID BIN MD ALI (University Kebangsaan Malaysia)
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10:00
ML and SoC-FPGA: Hardware assessment framework
30'
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08:00 - 10:00