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Place

Location: ICTP
Address: Via Grignano, 9 I - 34151 Trieste (Italy)
Room: Giambiagi Lecture Hall (AGH)
Date: 5 Dec 09:00 - 18:30

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09:00
10:00
11:00
12:00
13:00
14:00
15:00
16:00
17:00
18:00
SoC FPGA Design Verification and Timing Concepts
Adriatico Guest House - Giambiagi Lecture Hall, ICTP
Coffee break
Adriatico Guest House - Cafeteria, ICTP
Reconfigurable Virtual Instrumentation (RVI) based on SoC
Adriatico Guest House - Giambiagi Lecture Hall, ICTP
Lab activities with Tutors
Adriatico Guest House - Informatics Laboratory
Lunch break
Adriatico Guest House - Cafeteria, ICTP
From FPGA-based Reconfigurable Systems to Autonomic Heterogeneous Computing Systems
Adriatico Guest House - Giambiagi Lecture Hall, ICTP
Coffee break
Adriatico Guest House - Cafeteria, ICTP
Lab Tutorial: The RVI communication block (CommBlock)
Adriatico Guest House - Informatics Lab (Lower Level 1), ICTP

Organizers

Pirouz Bazargan Sabet (University Pierre Et Marie Curie, Paris, France), Nizar Abdallah (Microsemi Corp., California, USA), Andres Cicuttin (ICTP), Maria Liz Crespo (ICTP), Local Organiser: Maria Liz Crespo

Co-sponsors