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Displaying
58
contributions
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58
A Single Photon Detector System Based on Micropattern Gaseous Electron Multiplier
Session:
s_levorato_ICTP.pdf
AXI Custom IP
Session:
AXI_Bus_and_CustomIP.pdf
AXI data transfer caracterization in Zynq devices
Session:
Melo.pdf
Academic writing skills for research journal article
Session:
Article-Mamun-ICTP.pdf
Administrative procedure - registration and payments
Session:
All-Programmable System-on-Chip (SoC) technology
Session:
1_SoC.pdf
C for Embedded Systems
Session:
C for Embedded Systems (cont.)
Session:
5_C_4_Zynq_V1.pdf
Concluding Remarks and Distribution of Certificates
Session:
DEMO: A data acquisition and processing system based on SoC for particle detectors
Session:
DEMO: Thick-GEM based Particle Detector System: from Signal Generation to Data Acquisition and Processing
Session:
Design Methodology for SoC
Session:
3_Vivado_Embedded_System_Design_Flow.pdf
Digital arithmetic and numerical representations
Session:
FPGAs computing just right thanks to application-specific arithmetic
Session:
1-ComputingJustRight.pdf
Floating point operators: Square Root and Division
Session:
FreeRTOS operating system for SoC
Session:
FreeRTOS.pdf
From FPGA-based Reconfigurable Systems to Autonomic Heterogeneous Computing Systems
Session:
Santambrogio.pdf
Front-Ends and DAQ for Particle Physics experiments
Session:
DAQ_20181127.pdf
Fundamentals of Particle Detectors
Session:
Tessarotto.pdf
Hardware and Software Interrupts
Session:
6_Interrupts_Zynq.pdf
High Level Synthesis (HLS) I
Session:
Fernando_Rincon_Calle1.pdf
High Level Synthesis (HLS) II
Session:
Lab Tutorial: First steps with FreeRTOS
Session:
Lab_FreeRTOS_intro.pdf
Lab Tutorial: A PyQT GUI for a SoC design
Session:
Lab Tutorial: A PyQT GUI for a SoC design (cont)
Session:
Lab Tutorial: Building a complete Embedded System
Session:
Lab Tutorial: Custom AXI-Slave IP Core
Session:
Lab Tutorial: Design flow based on the processing system
Session:
Lab Tutorial: HLS and IDE Integration I
Session:
Fernando_Rincon_Calle2.pdf
Lab Tutorial: Hardware and Software Interrupts
Session:
Lab Tutorial: The RVI communication block (CommBlock)
Session:
Lab Tutorial: from HLS to a PyQT GUI with TCP/IP communication
Session:
Lab activities with Tutors
Session:
Lab activities with Tutors
Session:
Lab activities with Tutors
Session:
Lab activities with Tutors
Session:
Lab activities with Tutors
Session:
Lab activities with Tutors
Session:
Lab. Tutorial: Advanced project based on SoC
Session:
Lab. Tutorial: How to access the RVI CommBlock
Session:
Lab: HLS and IDE Integration II
Session:
Opening
Session:
PyQT for Graphical User Interface (GUI) Development
Session:
Jose_Antonio_De_La_Torre2.pdf
Python fundamentals
Session:
Jose_Antonio_De_La_Torre.pdf
Reconfigurable Virtual Instrumentation (RVI) based on SoC
Session:
Selected topics in digital design for FPGA
Session:
SoC FPGA Design Verification and Timing Concepts
Session:
TCP/IP communication with FreeRTOS
Session:
LwIP.pdf
TCP/IP communication: The LwIP library
Session:
The Era of All Programmable SoC: challenges for instrumentation and supercomputing I
Session:
The Era of All Programmable SoC: challenges for instrumentation and supercomputing II
Session:
The FloPoCo arithmetic core generator
Session:
2-FloPoCo.pdf
The RISK V architecture I
Session:
The RISK V architecture II
Session:
The SoC Architecture and Design Methodology
Session:
2_Zynq_Architecture_C7T.pdf
The Zynq Evaluation and Development Board
Session:
4_ZedBoard.pdf
The new generation of Intelligent FPGA based DAQ architectures
Session:
iFDAQ_20181128.pdf
Worskhop outline and ICTP programmes
Session:
smr3249-workshop_outline-MariaLiz.pdf
Organizers
Pirouz Bazargan Sabet (University Pierre Et Marie Curie, Paris, France), Nizar Abdallah (Microsemi Corp., California, USA), Andres Cicuttin (ICTP), Maria Liz Crespo (ICTP), Local Organiser: Maria Liz Crespo
Co-sponsors