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Displaying 10 authors out of 10
Night Laboratory
Hardware Description of the FPGA Development Platform
FPGA Development Platform. Design Examples
Selected topics on FPGA design I
Selected topics on FPGA design II
Selected topics on FPGA design III
FPGA Debugging
Reconfigurable Virtual Instrumentation I
Reconfigurable Virtual Instrumentation I
JOHANNES GRASSBERGER (SCS, ICTP, Trieste)
Network and Computing Facilities at ICTP
JORGEN CHRISTIANSEN (PH-ED, CERN, Geneva)
CMOS Technology I
CMOS Technology II & III
VLSI design I
VLSI design II & III
KONSTANTIN LUKIN (Usikov Institute of Radiophysics & Electronics, Kharkov)
Fourier Theory I
Fourier Theory II
Introduction to Digital Signal Processing
Digital Signal Processing and Radar applications I
Digital Signal Processing and Radar Applications I
Digital Signal Processing and Radar Applications III
Digital Signal Processing and Radar Applications IV
Digital Signal Processing and Radar applications V
MARIA LIZ CRESPO (ICTP, Trieste)
Laboratory Session
Laboratory Session (VHDL simulation environment, simple examples)
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory projects: Proposals and discussion
Laboratory projects: Proposals and discussion (cont)
Laboratory projects: Proposals and discussion (cont)
Laboratory projects: Proposals and discussion (cont)
Laboratory projects: Proposals and discussion (cont)
Laboratory projects: Proposals and discussion (cont)
Laboratory projects: Proposals and discussion (cont)
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session
Laboratory Session: Projects and Digital Signal Processing with FPGA
Course Overview, Introduction to FPGA Synthesis I, Introduction to VHDL
(LiberoTM IDE) Introduction to Actel Products. Libero IDE Overview and Design Flow
Synthesis II - Instroduction to VHDL
Synthesis III - Advanced VHDL
(LiberoTM IDE) Design Entry
(LiberoTM IDE) Functional Simulation. Synthesis
Synthesis III - Advanced VHDL (cont.)
(LiberoTM IDE) Place & Route
Design verification and timing concepts
(LiberoTM IDE) Timing Constraints and Analysis
Programmable logic & FPGA architectures
(LiberoTM IDE) Post-Layout Simulation. Programming
Actel Flash FPGA architecture
System-on-Chip concepts
DEMO Fusion
Q & A (open discussion)
PIROUZ BAZARGAN-SABET (LIP 6, University of Paris VI, Paris)
Introduction to Digital Design (Boolean Logic)
Digital Design I (Combinational Elements)
Digital Design II (Sequential Elements, Mealy and Moore FSM)
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
Digital arithmetic I (number representations)
Digital arithmetic II (basic operations: +,-,*,/)

Organizers

Directors: N. Abdallah, A. Cicuttin, A. Vacchi