VHDL for FPGA Design (cont.)
Place
Location: ICTP
Address: Via Grignano, 9
34151 - Trieste (Italy)
Room: Adriatico Guest House (Giambiagi Lecture Hall)
Date:
12 Nov 14:00 - 15:00
Timetable | Contribution List
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Organizers
A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo
ICTP Local Organizer: M.L. Crespo