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Contribution List

Displaying 58 contributions out of 58
Session: A primer on custom-precision floating-point arithmetic
Session: Advanced Applications of Digital Signal Processing
Session: Advanced SOC-FPGA trends
Session: Advanced SOC-FPGA trends (cont.)
Session: Advanced Scientific Applications of FPGA
Session: Advanced Topics in Digital Signal Processing
Session: Automated design of ASIP and accelerator based sub-systems for high-performance applications
Session: CMOS technology
Session: Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Session: Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Session: Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Session: Digital Design - Combinatorial elements
Session: Digital Design - More complex elements: RAM, ROM, buses, pipeline concept
Session: Digital Design - Sequential elements, Mealy and Moore FSM
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example.
Session: Digital arithmetic - Arithmetic operations
Session: Digital arithmetic - Number representations
Session: Digital filter design
Session: Digital processing of analog signals
Session: Digital signals and systems
Session: Discrete Fourier Transform
Session: Distribution of Certificates and Concluding Remarks
Session: Embedded system design for instrumentation using FPGA
Session: Evolution of Multicore Architectures: design strategies, languages and tools
Session: FPGA Debugging
Session: FPGA Design Implementation
Session: FPGA Design Implementation
Session: FPGA Design Implementation
Session: FPGA Design Techniques
Session: FPGA Technology
Session: FPGA Timing and Tools for High Performance
Session: Filter design examples
Session: Final Discussions
Session: Hardware Description of FPGA Development Platform
Session: High Level Synthesis: how to improve FPGA design productivity
Session: ISE WebPACK Design Software - Testbench - A Design Example
Session: Introduction to SoC Modeling
Session: Life at the edge: critical dynamics in the brain
Session: Microelectronics at CERN - Introduction to CMOS technology and VLSI Design
Session: OPENING and WELCOME
Session: Overview of Lab Sessions
Session: PC-FPGA Serial Communication - Design Example
Session: REGISTRATION AND ADMINISTRATIVE FORMALITIES
Session: Research Projects at the ICTP Mlab
Session: Research and Training at the ICTP Multidisciplinary Laboratory (ICTP Mlab)
Session: VHDL for FPGA Design
Session: VHDL for FPGA Design (cont.)
Session: VHDL for FPGA Design (contd.)
Session: VHDL for FPGA Design (contd.)
Session: VLSI Design
Session: VLSI Design (contd.)
Session: Wishbone IP Interface Standard

Organizers

A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo