Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
Place
Location: Kuala Lumpur - Malaysia
Date:
27 Jun 16:30 - 19:00
Timetable | Contribution List
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Presented by MARIA LIZ CRESPO
on
27/6/2008
at
16:30
Organizers
Directors: M.B.I. Reaz, S.C. Ng, A. Cicuttin, N. Abdallah, A. Marchioro, M.A.M. Ali, F. Mohd-Yasin, C. Oh, A.A. Halim