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Displaying 25 authors out of 25
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Advance FPGA Applications
Advance FPGA applications. A case study in HEP experiments
Advance FPGA applications. A case study in HEP experiments (contd)
Selected topics on Logic Synthesis and FPGA Debugging
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
System Design: Is Hardware Becoming Software?
Formal Verification Techniques for FPGA
Introduction to two-dimensional digital signal processing.
Two-dimensional digital signal processing I.
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
JASMINE NG (CADENCE)
Challenges in Low Power Design
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Introduction to Fourier Theory
Fourier Theory I
Fourier Theory II
Introduction to Digital Signal Processing
Digital Signal Processing I
Laboratory Session. VHDL Simulation Environment. A design example
Laboratory Session. VHDL Simulation Environment. A design example. Contd.
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
Laboratory Session. Finite State Machine: VHDL Description and Simulation
Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
Laboratory Session. RVI Architecture. Integration of new blocks
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
Introduction to FPGA Synthesis, Introduction to VHDL.
Introduction to ACETEL Products. Libero IDE Overview and Design flow
Synthesis I - Introduction to VHDL
Synthesis II - Introduction to VHDL
(LiberoTM IDE) Design Entry
(LiberoTM IDE) Functional Simulation. Synthesis
Synthesis III - Advanced VHDL
(LiberoTM IDE) Place & Route
Design Verification and Timing Concepts
(LiberoTM IDE) Timing Constraints and Analysis
Programmable logic & FPGA architectures
(LiberoTM IDE) Post-Layout Simulation. Programming
Actel Flash FPGA architecture
System-on-Chip concepts
DEMO Actel Fusion Evaluation Board
Course Overview
Microelectronics at CERN
Introduction to CMOS technology and VLSI design
CMOS Technology I
CMOS Technology II
VLSI Design I
VLSI design II
Digital Design II (sequential elements, Mealy and Moore FSM)
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
Digital arithmetic II (basic arithmetic operations)
Introduction to Digital Design (Boolean logic)
Digital Design I (combinatorial elements)
Digital arithmetic I (number representations)
STEPHEN BROWN (Director, Altera University Programme)
Effective FPGA/VLSI Education Techniques
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA

Organizers

Directors: M.B.I. Reaz, S.C. Ng, A. Cicuttin, N. Abdallah, A. Marchioro, M.A.M. Ali, F. Mohd-Yasin, C. Oh, A.A. Halim