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Contribution List

Displaying 101 contributions out of 101
Session: (LiberoTM IDE) Design Entry
Session: (LiberoTM IDE) Functional Simulation. Synthesis
Session: (LiberoTM IDE) Place & Route
Session: (LiberoTM IDE) Post-Layout Simulation. Programming
Session: (LiberoTM IDE) Timing Constraints and Analysis
Session: Actel Flash FPGA architecture
Session: Advance FPGA Applications
Session: Advance FPGA applications. A case study in HEP experiments
Session: Advance FPGA applications. A case study in HEP experiments (contd)
Session: Altera-MDEC FPGA Education Launch
Session: An Overview of Microprocessor Architecture & Implementation of a Large Bus Size VLIW Microprocessor on FPGA.
Session: An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
Session: CMOS Technology I
Session: CMOS Technology II
Session: Certificates of Participation (DK E)
Session: Challenges in Low Power Design
Session: Closing Ceremony (UA113, Sport Complex)
Session: Course Overview
Session: DEMO Actel Fusion Evaluation Board
Session: Design Verification and Timing Concepts
Session: Digital Design I (combinatorial elements)
Session: Digital Design II (sequential elements, Mealy and Moore FSM)
Session: Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
Session: Digital Signal Processing I
Session: Digital arithmetic I (number representations)
Session: Digital arithmetic II (basic arithmetic operations)
Session: Effective FPGA/VLSI Education Techniques
Session: Formal Verification Techniques for FPGA
Session: Fourier Theory I
Session: Fourier Theory II
Session: Introduction
Session: Introduction to ACETEL Products. Libero IDE Overview and Design flow
Session: Introduction to CMOS technology and VLSI design
Session: Introduction to Digital Design (Boolean logic)
Session: Introduction to Digital Signal Processing
Session: Introduction to FPGA Synthesis, Introduction to VHDL.
Session: Introduction to Fourier Theory
Session: Introduction to two-dimensional digital signal processing.
Session: Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
Session: Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
Session: Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
Session: Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Session: Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Session: Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
Session: Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
Session: Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
Session: Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
Session: Laboratory Session. Finite State Machine: VHDL Description and Simulation
Session: Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
Session: Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
Session: Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
Session: Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
Session: Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
Session: Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
Session: Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
Session: Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Session: Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Session: Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
Session: Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
Session: Laboratory Session. RVI Architecture. Integration of new blocks
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Session: Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
Session: Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
Session: Laboratory Session. VHDL Simulation Environment. A design example
Session: Laboratory Session. VHDL Simulation Environment. A design example. Contd.
Session: Microelectronics at CERN
Session: Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
Session: Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
Session: Open Discussion
Session: Opening Ceremony
Session: Programmable logic & FPGA architectures
Session: REGISTRATION AND ADMIN FORMALITIES
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
Session: SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
Session: SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
Session: Selected topics on Logic Synthesis and FPGA Debugging
Session: Selected topics on Logic Synthesis and FPGA Debugging (cont.)
Session: Synthesis I - Introduction to VHDL
Session: Synthesis II - Introduction to VHDL
Session: Synthesis III - Advanced VHDL
Session: System Design: Is Hardware Becoming Software?
Session: System-on-Chip concepts
Session: Two-dimensional digital signal processing I.
Session: Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
Session: Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
Session: VLSI Design I
Session: VLSI design II
Session: Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
Session: Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
Session: Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.

Organizers

Directors: M.B.I. Reaz, S.C. Ng, A. Cicuttin, N. Abdallah, A. Marchioro, M.A.M. Ali, F. Mohd-Yasin, C. Oh, A.A. Halim