Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Place
Location: ICTP
Address: Via Grignano, 9
34151 - Trieste (Italy)
Room: Adriatico Guest House (Giambiagi Lecture Hall)
Date:
13 Nov 17:30 - 19:00
Timetable | Contribution List
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Session:
Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Presented by KRISHNA M. KHARE, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
on
13/11/2013
at
17:30
Organizers
A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo
ICTP Local Organizer: M.L. Crespo