Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Place
Location: ICTP
Address: Via Grignano, 9
34151 - Trieste (Italy)
Room: Adriatico Guest House (Giambiagi Lecture Hall)
Date:
14 Nov 15:30 - 18:30
Timetable | Contribution List
Displaying 1
contribution
out of
1
Session:
Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Presented by KRISHNA M. KHARE, THULASIRAMAN NANDHA KUMAR, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
on
14/11/2013
at
15:30
Organizers
A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo
ICTP Local Organizer: M.L. Crespo