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VHDL for FPGA Design

Place

Location: ICTP
Address: Via Grignano, 9 34151 - Trieste (Italy)
Room: Adriatico Guest House (Giambiagi Lecture Hall)
Date: 11 Nov 17:30 - 18:30

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Displaying 1 contribution out of 1
Presented by CRISTIAN SISTERNA on 11/11/2013 at 17:30
Building timetable...

Organizers

A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo