First ICTP Regional Microelectronics Workshop and Training on VHDL for Hardware Synthesis and FPGA Design in Asia-Pacific

. JIMMY YEAP

Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.

ALEXANDER KLUGE

Advance FPGA Applications

Advance FPGA applications. A case study in HEP experiments

Advance FPGA applications. A case study in HEP experiments (contd)

ANDRES CICUTTIN

Selected topics on Logic Synthesis and FPGA Debugging

Selected topics on Logic Synthesis and FPGA Debugging (cont.)

Reconfigurable Virtual Instrumentation (RVI) based on FPGA

Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)

CARLOS SOSA PAEZ

Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.

Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)

CHEW BENG WAH

Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon

CHEW BENG WAN

Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.

CHOONG YEE LEE

Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage

CHRIS OH

System Design: Is Hardware Becoming Software?

ELISHA LYE

Formal Verification Techniques for FPGA

FABIO MAMMANO

Introduction to two-dimensional digital signal processing.

Two-dimensional digital signal processing I.

Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I

Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II

JASMINE NG (CADENCE)

Challenges in Low Power Design

JIMMY YEAP

Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.

KHAN JAVED IQBAL

Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I

Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II

KING KEONG WANG, THIAM SIN LAI

Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits

KING KEONG WONG, THIAM SIN LAI

Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits

MARCELO MAGNASCO

Introduction to Fourier Theory

Fourier Theory I

Fourier Theory II

Introduction to Digital Signal Processing

Digital Signal Processing I

MARIA LIZ CRESPO

Laboratory Session. VHDL Simulation Environment. A design example

Laboratory Session. VHDL Simulation Environment. A design example. Contd.

Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits

Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.

Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits

Laboratory Session. Finite State Machine: VHDL Description and Simulation

Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation

Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)

Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)

Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.

Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.

Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.

Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA

Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.

MIGUEL RISCO CASTILLO

Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.

Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)

Laboratory Session. RVI Architecture. Integration of new blocks

Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.

NIZAR ABDALLAH

Introduction to FPGA Synthesis, Introduction to VHDL.

Introduction to ACETEL Products. Libero IDE Overview and Design flow

Synthesis I - Introduction to VHDL

Synthesis II - Introduction to VHDL

(LiberoTM IDE) Design Entry

(LiberoTM IDE) Functional Simulation. Synthesis

Synthesis III - Advanced VHDL

(LiberoTM IDE) Place & Route

Design Verification and Timing Concepts

(LiberoTM IDE) Timing Constraints and Analysis

Programmable logic & FPGA architectures

(LiberoTM IDE) Post-Layout Simulation. Programming

Actel Flash FPGA architecture

System-on-Chip concepts

DEMO Actel Fusion Evaluation Board

NIZAR ABDALLAH, ANDRES CICUTTIN (ACTEL, ICTP)

Course Overview

PAULO MOREIRA

Microelectronics at CERN

Introduction to CMOS technology and VLSI design

CMOS Technology I

CMOS Technology II

VLSI Design I

VLSI design II

PIROUZ BAZARGAN-SABAT

Digital Design II (sequential elements, Mealy and Moore FSM)

Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)

Digital arithmetic II (basic arithmetic operations)

PIROUZ BAZARGAN-SABET

Introduction to Digital Design (Boolean logic)

Digital Design I (combinatorial elements)

Digital arithmetic I (number representations)

STEPHEN BROWN (Director, Altera University Programme)

Effective FPGA/VLSI Education Techniques

WENG FOOK LEE

An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA

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