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Displaying 12 speakers out of 12
ALEXANDER KLUGE (CERN, Geneva, Switzerland)
Advanced FPGA Applications.
A case study in HEP experiments I.
A case study in HEP experiments II
A case study in HEP experiments III
ANDRES AIRABELLA (University of San Luis, Argentina)
ICTP RVI Platform Description.
Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter).
ANDRES CICUTTIN
Selected topics on Logic Synthesis and FPGA Debugging.
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
Reconfigurable Virtual Instrumentation (RVI) based on FPGA.
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
CARLOS SOSA PAEZ (University of San Luis, Argentina)
Hardware Description of the FPGA Development Platform.
Digital Signal Processing with FPGA. A Design Example: Differentiator.
Digital Signal Processing with FPGA. A Design Example: Differentiator (cont.)
CRISTIAN SISTERNA (University of San Juan, Argentina)
Basic Add and Subtract Operations in VHDL. Case examples.
FPGA Implementation Example.
FELIX PALUMBO (CONICET - CNEA, Buenos Aires)
Radiation Effects in Semiconductor Devices.
Radiation Effects in Semiconductor Devices.
MARCELO MAGNASCO (Rockfeller University, NY, USA)
Introduction to Fourier Theory.
Fourier Theory I.
Fourier Theory II.
Introduction to Digital Signal Processing.
Digital Signal Processing I
Digital Signal Processing II
MARIA LIZ CRESPO (ICTP Multidisciplinary Laboratory, Trieste, Italy)
Laboratory Overview. VHDL Simulation Environment. A design example.
Advanced Data Acquisition and Processing System for a HEP Experiment at CERN
MIGUEL RISCO CASTILLO
The µLab Virtual Panel. A design example.
DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope
NIZAR ABDALLAH
FPGA Design and VHDL. Overview.
FPGA Architectures & VHDL. Introduction to FPGAs & FPGA Design Flow.
FPGA Architectures & VHDL. Introduction to Synthesis.
Synthesis II - Introduction to VHDL.
(LiberoTM IDE) Design Entry.
(LiberoTM IDE) Functional Simulation. Synthesis.
Synthesis III - Advanced VHDL.
(LiberoTM IDE) Place & Route.
Design Verification and Timing Concepts.
(LiberoTM IDE) Timing Constraints and Analysis
Programmable logic & FPGA architectures
(LiberoTM IDE) Post-Layout Simulation. FPGA Programming.
Actel Fusion FPGA architecture.
Actel Fusion FPGA architecture (cont.)
The Actel Fusion Embedded Development Kit
The Actel Fusion Embedded Development Kit (cont.)
System-on-Chip concepts
System-on-Chip concepts (cont.)
PAULO RODRIGUES S. MOREIRA (CERN, Geneva, Switzerland)
Microelectronics at CERN
Introduction to CMOS Technology and VLSI Design.
CMOS Technology I
CMOS Technology II.
VLSI Design.
PIROUZ BAZARGAN-SABET (LIP6, University Pierre et Matie Curie, Paris, France)
Introduction to Digital Design.
Digital Design I (combinatorial elements).
Digital Design II (sequential elements, Mealy and Moore FSM).
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc).
Digital arithmetic I (number representations).
Digital arithmetic II (basic arithmetic operations).

Organizers

Directors: A. Cicuttin, N. Abdallah, H. Larrondo, L. H. Tabares. LO: J. Finochietto, C. Gonzalez. ICTP LO: M.L. Crespo.