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Displaying 21 speakers out of 21
ABELARDO JARA-BERROCAL (Megh Computing, USA)
Introduction to Parallel Computing using FPGAs
Writing OpenCL programs for FPGAs
Optimizing OpenCL programs for FPGAs
Software Application Stack for FPGAs (OPAE and SIRA)
Developing and Debugging RTL-based Accelerator Units on FPGAs
ANDRES CICUTTIN (ICTP)
From Advanced Instrumentation Towards Supercomputing
BRUNO VALINOTI (Instituto Nacional de Tecnologia Industrial, Argentina)
Lab. Tutorial: How to access the SoC from a host computer
CRISTIAN SISTERNA (UNSJ, Argentina)
All-Programmable System-on-Chip (SoC) technology
The SoC Architecture and Design Methodology
Evaluation and Development Board (Zedboard)
C for Embedded Systems
AXI Custom IP
ENRICO CALORE (Janus, University of Ferrara)
EuroEXA project and FPGAs
FERNANDO RINCON CALLE (UCLM, Spain)
FreeRTOS operating system for SoC
TCP/IP communication: The LwIP library
Lab Tutorial: First steps with FreeRTOS & LwIP library
FLORENT DE DINECHIN (Lyon, France)
The FloPoCo arithmetic core generator
FPGAs computing just right thanks to application-specific arithmetic
GRZEGORZ PASTUSZAK (Warsaw University of Technology, Warsaw, Poland)
Feature Extraction from Waveforms and Data Compression
IGOR KONOROV (TUM, Munich)
Front-Ends and DAQ for Particle Physics experiments
The new generation of Intelligent FPGA based DAQ architectures
IVAN GIROTTO (ICTP)
High-Performance Computing at the ICTP
KASUN S. MANNATUNGA (University of Moratuwa, Sri Lanka)
Lab Tutorial: Advanced project based on SoC for Scientific Computing
LUIS GARCIA ORDONEZ (ICTP / Guatemala)
Lab Tutorial: Custom AXI IP Core
Lab Tutorial: FloPoCo for Scientific Computing
MARIA LIZ CRESPO (ICTP)
Workshop Outline
MARIA LIZ CRESPO (ICTP), ANDRES CICUTTIN (ICTP)
Concluding Remarks and Distribution of Certificates
MIRKO MARIOTTI (University of Perugia, Perugia)
BondMachine, a mouldable computer architecture
BondMachine, a mouldable computer architecture (cont.)
NIZAR ABDALLAH (Microsemi, San Diego, USA)
The Era of All Programmable SoC: challenges for supercomputing
The RISK V architecture
The RISK V architecture (cont.)
PIROUZ BAZARGAN SABET (LIP6, Paris, France)
Digital arithmetic and numerical representations
Floating point operators: Square Root and Division
RODRIGO MELO (INTI, Argentina)
Lab Tutorial: Data transfer with DMA
Lab Tutorial: FPGA-Processor Interface
ROMINA MOLINA (UNSL, Argentina)
Lab Tutorial: Building a complete Embedded System
SANDRO SCANDOLO (ICTP), ANDRES CICUTTIN (ICTP), MARIA LIZ CRESPO (ICTP)
Welcome to the Workshop
SEBASTIANO FABIO SCHIFANO (Janus, University of Ferrara)
The JANUS project

Organizers

Andres Cicuttin (ICTP), Maria Liz Crespo (ICTP), Local Organiser: Maria Liz Crespo

Co-sponsors