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Displaying 24 speakers out of 24
ALEXANDER KLUGE (CERN, Geneva, Switzerland)
Advanced Scientific Applications of FPGA
ANDRES CICUTTIN (ICTP, Trieste, Italy)
FPGA Debugging
Wishbone IP Interface Standard
ANDRES CICUTTIN, MARIA LIZ CRESPO, JULIO D. DONDO GAZZANO
Distribution of Certificates and Concluding Remarks
ANDRES CICUTTIN, MARIA LIZ CRESPO, JULIO DONDO GAZZANO
OPENING and WELCOME
CARLOS SOSA PAEZ (University of San Luis, San Luis, Argentina)
Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example.
CARLOS VALDERRAMA (Polytechnique of Mons, Mons, Belgium)
Evolution of Multicore Architectures: design strategies, languages and tools
CRISTIAN SISTERNA (University of San Juan, San Juan, Argentina)
FPGA Technology
FPGA Design Techniques
FPGA Timing and Tools for High Performance
VHDL for FPGA Design
VHDL for FPGA Design (cont.)
VHDL for FPGA Design (contd.)
VHDL for FPGA Design (contd.)
ISE WebPACK Design Software - Testbench - A Design Example
FERNANDO RINCON CALLE (Universty of Castilla-La Mancha, Spain)
High Level Synthesis: how to improve FPGA design productivity
JULIO DONDO GAZZANO (Universty of Castilla-La Mancha, Spain)
Introduction to SoC Modeling
KRISHNA M. KHARE, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
KRISHNA M. KHARE, THULASIRAMAN NANDHA KUMAR, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
Combinational and Sequential Logic Described in VHDL - Description, Synthesis and Simulation
FPGA Design Implementation
FPGA Design Implementation
FPGA Design Implementation
Digital Signal Processing with FPGA
KRISHNA MOHAN KHARE
Embedded system design for instrumentation using FPGA
LECH JOZWIAK (Eindhoven University of Technology, Eindhoven, The Netherlands)
Automated design of ASIP and accelerator based sub-systems for high-performance applications
MANFRED MUECKE (Sustainable Computing Research, Vienna, Austria)
A primer on custom-precision floating-point arithmetic
MARCELO MAGNASCO (Rockfeller Uinveristy, NYC, USA)
Life at the edge: critical dynamics in the brain
Advanced Topics in Digital Signal Processing
Advanced Applications of Digital Signal Processing
MARIA LIZ CRESPO (ICTP, Trieste, Italy)
Overview of Lab Sessions
Research and Training at the ICTP Multidisciplinary Laboratory (ICTP Mlab)
MASSIMILIANO NOLICH (Università degli Studi di Trieste, Trieste, Italy)
Digital signals and systems
Digital processing of analog signals
Discrete Fourier Transform
Digital filter design
Filter design examples
MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
Digital Signal Processing with FPGA
Digital Signal Processing with FPGA
Digital Signal Processing with FPGA
MIGUEL RISCO CASTILLO (Technological University of Peru, Lima , Peru)
Hardware Description of FPGA Development Platform
NIZAR ABDALLAH (Microsemi, Mountain View, CA, USA)
Advanced SOC-FPGA trends
Advanced SOC-FPGA trends (cont.)
PIROUZ BAZARGAN-SABET (Unviersity Pierre & Marie Curie, Paris, France)
Digital Design - Combinatorial elements
Digital Design - Sequential elements, Mealy and Moore FSM
Digital Design - More complex elements: RAM, ROM, buses, pipeline concept
Digital arithmetic - Number representations
Digital arithmetic - Arithmetic operations
SANDRO BONACINI (CERN, Geneva, Switzerland)
Microelectronics at CERN - Introduction to CMOS technology and VLSI Design
CMOS technology
VLSI Design
VLSI Design (contd.)
THULASIRAMAN NANDHA KUMAR (The University of Nottingham, Malaysia Campus, Selangor, Malaysia)
PC-FPGA Serial Communication - Design Example
THULASIRAMAN NANDHA KUMAR, MIGUEL A. RISCO CASTILLO, CRISTIAN A. SISTERNA , CARLOS F. SOSA PAEZ
Digital Signal Processing with FPGA
Digital Signal Processing with FPGA

Organizers

A. Cicuttin, M.L. Crespo (ICTP MLab, Trieste), J.D. Dondo (Spain).
ICTP Local Organizer: M.L. Crespo