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Contribution List

Displaying 79 contributions out of 79
Session: (LiberoTM IDE) Design Entry.
Session: (LiberoTM IDE) Functional Simulation. Synthesis.
Session: (LiberoTM IDE) Place & Route.
Session: (LiberoTM IDE) Post-Layout Simulation. FPGA Programming.
Session: (LiberoTM IDE) Timing Constraints and Analysis
Session: A case study in HEP experiments I.
Session: A case study in HEP experiments II
Session: A case study in HEP experiments III
Session: Actel Fusion FPGA architecture (cont.)
Session: Actel Fusion FPGA architecture.
Session: Advanced Data Acquisition and Processing System for a HEP Experiment at CERN
Session: Advanced FPGA Applications.
Session: Basic Add and Subtract Operations in VHDL. Case examples.
Session: CMOS Technology I
Session: CMOS Technology II.
Session: DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope
Session: Design Verification and Timing Concepts.
Session: Digital Design I (combinatorial elements).
Session: Digital Design II (sequential elements, Mealy and Moore FSM).
Session: Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc).
Session: Digital Signal Processing I
Session: Digital Signal Processing II
Session: Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter) (contd).
Session: Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter).
Session: Digital Signal Processing with FPGA. A Design Example: Differentiator.
Session: Digital Signal Processing with FPGA. A Design Example: Differentiator (cont.)
Session: Digital arithmetic I (number representations).
Session: Digital arithmetic II (basic arithmetic operations).
Session: Distribution of Diplomas of Attendance
Session: FPGA Architectures & VHDL. Introduction to FPGAs & FPGA Design Flow.
Session: FPGA Architectures & VHDL. Introduction to Synthesis.
Session: FPGA Design and VHDL. Overview.
Session: FPGA Implementation Example.
Session: Fourier Theory I.
Session: Fourier Theory II.
Session: General Discussions and Concluding Remarks
Session: Hardware Description of the FPGA Development Platform.
Session: ICTP RVI Platform Description.
Session: Introduction to CMOS Technology and VLSI Design.
Session: Introduction to Digital Design.
Session: Introduction to Digital Signal Processing.
Session: Introduction to Fourier Theory.
Session: Laboratory Exercises: Digital Arithmetic.
Session: Laboratory Exercises: Digital Signal Processing with FPGA.
Session: Laboratory Exercises: Digital Signal Processing with FPGA.
Session: Laboratory Exercises: Digital Signal Processing with FPGA. (contd.)
Session: Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation (cont.)
Session: Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation.
Session: Laboratory Exercises: Finite State Machine. VHDL Description and Simulation (cont.)
Session: Laboratory Exercises: Finite State Machine. VHDL Description and Simulation.
Session: Laboratory Exercises: Implementation in the FPGA Development Platform (cont.)
Session: Laboratory Exercises: Implementation in the FPGA Development Platform (contd.)
Session: Laboratory Exercises: Implementation in the FPGA Development Platform.
Session: Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
Session: Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
Session: Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits.
Session: Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits
Session: Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits (cont.)
Session: Laboratory Exercises: Waveform generation
Session: Laboratory Overview. VHDL Simulation Environment. A design example.
Session: Microelectronics at CERN
Session: OPENING CEREMONY
Session: Programmable logic & FPGA architectures
Session: REGISTRATION AND ADMINISTRATIVE FORMALITIES
Session: Radiation Effects in Semiconductor Devices.
Session: Radiation Effects in Semiconductor Devices.
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA.
Session: Selected topics on Logic Synthesis and FPGA Debugging (cont.)
Session: Selected topics on Logic Synthesis and FPGA Debugging.
Session: Synthesis II - Introduction to VHDL.
Session: Synthesis III - Advanced VHDL.
Session: System-on-Chip concepts
Session: System-on-Chip concepts (cont.)
Session: The Actel Fusion Embedded Development Kit
Session: The Actel Fusion Embedded Development Kit (cont.)
Session: The µLab Virtual Panel. A design example.
Session: The µLab Virtual Panel. A design example. (contd).
Session: VLSI Design.

Organizers

Directors: A. Cicuttin, N. Abdallah, H. Larrondo, L. H. Tabares. LO: J. Finochietto, C. Gonzalez. ICTP LO: M.L. Crespo.