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Displaying 15 speakers out of 15
A. CICUTTIN (ICTP)
Course Overview
Selected Topics on Logic Synthesis and FPGA Debugging
Selected Topics on Logic Synthesis and FPGA Debugging (cont.)
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
A. KLUGE (CERN, Geneva, Switzerland)
Advanced FPGA Applications
A case study in HEP experiments (I)
A case study in HEP experiments (II)
A case study in HEP experiments (III)
C. SISTERNA (UNSJ, San Juan, Argentina)
Laboratory Session. FPGA Implementation Example.
Advanced VHDL Subjects
Advanced FPGA Subjects
Advanced FPGA Subjects (cont.)
C. SOSA PAEZ (UNSL, San Luis, Argentina)
Laboratory Session. Hardware Description of the FPGA Development Platform.
Laboratory Session. Hardware Description of the FPGA Development Platform (cont.)
Laboratory Session: Digital Signal Processing with FPGA. A design example.
C.TUNIZ (Assistant Director, ICTP)
Opening Address
F. MAMMANO (University of Padova, Italy)
Introduction to two-dimensional digital signal processing
Two-dimensional digital signal processing
Three-dimensional deconvolution in FPGA
K.M. KHARE (RRCAT, Indore, India)
FPGA-based Custom Board Design for Instrumentation
Laboratory Session: ICTP RVI Platform Description
Laboratory Session: ICTP RVI Platform. A Design Example.
M. L. CRESPO
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
Laboratory Session. Digital Arithmetic.
Laboratory Session. Digital Arithmetic (cont.)
M. NOLICH (University of Trieste, Italy)
Introduction to Digital Signal Processing
Discrete Time Signals and Systems
The Z-Transform
Sampling of Continuous-Time Signals
The Discrete Fourier Transform
Transform Analysis of LTI Systems
Digital Filters Design
Digital Filters Design (cont.)
M. RISCO CASTILLO
The µLab Virtual Pannel. A design example.
M. RISCO CASTILLO, J. LOPEZ BOTERO
Laboratory Session: DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope (cont.)
M.A. RISCO CASTILLO (Technological University of Peru, Lima, Peru)
The µLab Virtual Pannel
M.L. CRESPO
Laboratory Session. VHDL Simulation Environment. A design example
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits.
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits.
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits (Cont.)
Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
Laboratory Session. Synthesis and Post-Synthesis Simulation
Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Laboratory Session. Implementation in the FPGA Development Platform
Laboratory Session: Waveform generation
Laboratory Session: Waveform generation (cont.)
N. ABDALLAH (Actel Corp., CA, USA)
Course Introduction
Introduction to FPGA Synthesis. Introduction to VHDL
Introduction to Actel Prodcuts. Libero IDE Overview and Design Flow
Sinthesis I - Introduction to VHDL
Sinthesis II - Introduction to VHDL
(LiberoTM IDE) Design Entry
(LiberoTM IDE) Functional Simulation. Synthesis
Synthesis III - Advanced VHDL
(LiberoTM IDE) Place & Route
Design Verification and Timing Concepts
(LiberoTM IDE) Timing Constraints and Analysis
Programmable logic & FPGA architectures
(LiberoTM IDE) Post-Layout Simulation. Programming
Actel Fusion FPGA Architecture
Actel Fusion FPGA Architecture (cont.)
The Actel Fusion Embedded Development Kit
The Actel Fusion Embedded Development Kit (cont.)
System-on-Chip Concepts.
System-on-Chip Concepts (cont.)
P. BAZARGAN-SABET (University Pierre & Marie Curie, LIP6, Paris, France)
Introduction to Digital Design
Digital Design I (Combinatorial elements)
Digital Design II (Sequential elements, Mealy and Moore FSM)
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
Digital arithmetic I (number representations)
Digital arithmetic II (basic arithmetic operations)

Organizers

Directors: N. Abdallah, A. Cicuttin, A. Marchioro. Local Organizer: M.L. Crespo