Scientific Calendar Event
GO TO SCIENTIFIC CALENDAR



  • Europe/Rome
  • English
  • Administration

Search

Search in Conferences:

Support

Home > Contribution List

Contribution List

Displaying 95 contributions out of 95
Session: (LiberoTM IDE) Design Entry
Session: (LiberoTM IDE) Functional Simulation. Synthesis
Session: (LiberoTM IDE) Place & Route
Session: (LiberoTM IDE) Post-Layout Simulation. Programming
Session: (LiberoTM IDE) Timing Constraints and Analysis
Session: A case study in HEP experiments (I)
Session: A case study in HEP experiments (II)
Session: A case study in HEP experiments (III)
Session: Actel Fusion FPGA Architecture
Session: Actel Fusion FPGA Architecture (cont.)
Session: Advanced FPGA Applications
Session: Advanced FPGA Subjects
Session: Advanced FPGA Subjects (cont.)
Session: Advanced VHDL Subjects
Session: Course Introduction
Session: Course Overview
Session: Darwin & Modern Science
Session: Design Verification and Timing Concepts
Session: Digital Design I (Combinatorial elements)
Session: Digital Design II (Sequential elements, Mealy and Moore FSM)
Session: Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
Session: Digital Filters Design
Session: Digital Filters Design (cont.)
Session: Digital arithmetic I (number representations)
Session: Digital arithmetic II (basic arithmetic operations)
Session: Discrete Time Signals and Systems
Session: Distribution of Diplomas of Attendance
Session: FPGA-based Custom Board Design for Instrumentation
Session: Introduction to Actel Prodcuts. Libero IDE Overview and Design Flow
Session: Introduction to Digital Design
Session: Introduction to Digital Signal Processing
Session: Introduction to FPGA Synthesis. Introduction to VHDL
Session: Introduction to two-dimensional digital signal processing
Session: Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Session: Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Session: Laboratory Session. Synthesis and Post-Synthesis Simulation (cont.)
Session: Laboratory Session. Digital Arithmetic (cont.)
Session: Laboratory Session. Digital Arithmetic.
Session: Laboratory Session. FPGA Implementation Example.
Session: Laboratory Session. Hardware Description of the FPGA Development Platform (cont.)
Session: Laboratory Session. Hardware Description of the FPGA Development Platform.
Session: Laboratory Session. Implementation in the FPGA Development Platform
Session: Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
Session: Laboratory Session. Laboratory Session. Finite State Machine: VHDL Description and Simulation (cont.)
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
Session: Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
Session: Laboratory Session. Synthesis and Post-Synthesis Simulation
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits.
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits (Cont.)
Session: Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits.
Session: Laboratory Session. VHDL Simulation Environment. A design example
Session: Laboratory Session: DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope (cont.)
Session: Laboratory Session: Digital Signal Processing with FPGA. A design example.
Session: Laboratory Session: ICTP RVI Platform Description
Session: Laboratory Session: ICTP RVI Platform. A Design Example.
Session: Laboratory Session: Waveform generation
Session: Laboratory Session: Waveform generation (cont.)
Session: Opening Address
Session: Presentation of FPGA Projects by Participants and Discussion
Session: Presentation of FPGA Projects by Participants and Discussion
Session: Presentation of FPGA Projects by Participants and Discussion
Session: Presentation of FPGA Projects by Participants and Discussion (cont.)
Session: Programmable logic & FPGA architectures
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
Session: Sampling of Continuous-Time Signals
Session: Selected Topics on Logic Synthesis and FPGA Debugging
Session: Selected Topics on Logic Synthesis and FPGA Debugging (cont.)
Session: Sinthesis I - Introduction to VHDL
Session: Sinthesis II - Introduction to VHDL
Session: Synthesis III - Advanced VHDL
Session: System-on-Chip Concepts (cont.)
Session: System-on-Chip Concepts.
Session: The Actel Fusion Embedded Development Kit
Session: The Actel Fusion Embedded Development Kit (cont.)
Session: The Discrete Fourier Transform
Session: The Z-Transform
Session: The µLab Virtual Pannel
Session: The µLab Virtual Pannel. A design example.
Session: Three-dimensional deconvolution in FPGA
Session: Transform Analysis of LTI Systems
Session: Two-dimensional digital signal processing
Session: Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB)
Session: Visit to and Presentation of the ICTP Multidisciplinary Laboratory (ICTP-MLAB)

Organizers

Directors: N. Abdallah, A. Cicuttin, A. Marchioro. Local Organizer: M.L. Crespo