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Registration Formalities
Displaying
75
contributions
out of
75
Advanced SoC-FPGA Topics
Session:
C for Embedded Systems
Session:
Coffee Break
Session:
Coffee Break
Session:
Design Methodology for FPGA-based System on Chip
Session:
Development Board: Zynq SoC
Session:
Digital Pulse Processing for Isotope Identification
Session:
Digital Pulse Processing for X-ray Photon Detection and Energy Measurement
Session:
Digital Pulse Processor: Main Functional Blocks - Part I
Session:
Digital Pulse Processor: Main Functional Blocks - Part II
Session:
Distribution of Certificates and Closing Remarks
Session:
Edge AI Applications on FPGA-Based Systems
Session:
Edge AI for the Internet of Things: Insights from Real-World Projects
Session:
Embedded Linux on SoC-FPGA
Session:
Embedded Real-Time Operating System
Session:
End-to-End Dataset Generation for Machine Learning
Session:
Fundamentals of Applied Machine Learning
Session:
Green Intelligence at the Edge: Sustainable Hardware for AI
Session:
Guide for Final Project - Part I
Session:
Guide for Final Project - Part II
Session:
Guide for Lab 1 - Getting Started with SoC
Session:
Guide for Lab 2 - Reconfigurable Instrumentation on SoC-FPGA
Session:
Guide for Lab 3 - SoC-FPGA Development Framework
Session:
Guide for Lab 6: Pulse Acquisition and Detector Characterization
Session:
Guide for Lab 7: Digital Pulse Processor (DPP)
Session:
Handling High Event Rates and Pile-Up - Part I
Session:
Handling High Event Rates and Pile-Up - Part II
Session:
Hardware Description Language for Reconfigurable Instrumentation
Session:
Hardware-Software Co-Design
Session:
High Event-Rate Discrimination on Mixed Radiation Fields with Machine Learning
Session:
High-Level Synthesis (HLS) – Part I
Session:
High-Level Synthesis (HLS) – Part II
Session:
Hog: An Open-Source Tool for Managing HDL Repositories on Git
Session:
HyperFPGA: Heterogeneous Computing on MPSoC-FPGA at ICTP
Session:
IAEA Programmes & NSIL Activities
Session:
ICTP Programmes & MLab Activities
Session:
ICTP-IAEA MA-XRF Scanner
Session:
Integrating Intelligence in 5G: How ML and AI Are Shaping 5G Networks?
Session:
Integrating Machine Learning into Digital Pulse Processing
Session:
Introduction to AI-Enabled Semantic and Goal-Oriented Communications for the Internet of Things
Session:
Introduction to Machine Learning and Edge AI
Session:
Lab 1 with tutors
Session:
Lab 1 with tutors
Session:
Lab 2 with tutors
Session:
Lab 2 with tutors
Session:
Lab 3 with tutors
Session:
Lab 3 with tutors
Session:
Lab 4.1: Training Machine Learning Models
Session:
Lab 4.2: Applying Model Compression Techniques
Session:
Lab 5.1: Integrating ML Models with HLS4ML for Hardware Synthesis
Session:
Lab 5.2: Deploying Machine Learning Models on SoC-FPGA
Session:
Lab 6 with tutors
Session:
Lab 6 with tutors
Session:
Lab 7 with tutors
Session:
Lab 7 with tutors
Session:
Model Optimization and Compression Techniques
Session:
Opening Remarks
Session:
Peripheral Interfaces & IP Integration
Session:
Programmable System on Chip (PSoC) Architecture
Session:
Project Lab with Tutors
Session:
Project Lab with tutors
Session:
Project Lab with tutors
Session:
Project lab with tutors
Session:
Pulse Acquisition and Detector Characterization
Session:
School Outline
Session:
Semiconductors and Collaboration: Building Pathways for Innovation and Talent
Session:
SoC: A Practical Implementation Overview on Intelligent Neurosystems
Session:
The Open Standard RISC-V Architecture - Part I
Session:
The Open Standard RISC-V Architecture - Part II
Session:
Using FPGAs to Accelerate Machine Learning Algorithms
Session:
Virtual Machine and User Environment
Session:
When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part I
Session:
When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part II
Session:
coffee-break
Session:
coffee-break
Session:
Organizers
Mladen Bogovac (IAEA, Austria), Maria Liz Crespo (ICTP, Italy), Kalliopi Kanaki (IAEA, Austria), Local Organiser: Maria Liz Crespo (ICTP)
Co-sponsors