Joint ICTP-IAEA School on Detector Signal Processing and Machine Learning for Scientific Instrumentation and Reconfigurable Computing | (smr 4110) (27 October 2025

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Displaying 77 contributions out of 77

Advanced SoC-FPGA Topics

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- advanced_topics.pdf

C for Embedded Systems

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- C_for_Embedded_Systems_2.pdf

Coffee Break

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Coffee Break

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Design Methodology for FPGA-based System on Chip

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- design_methodology.pdf

Development Board: Zynq SoC

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- Development_Board_Zynq_SoC_copy.pdf

Digital Pulse Processing for Isotope Identification

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- SMR4100_Mladen_Bogovac_DPP_for_Isotope_Identification.pdf

Digital Pulse Processing for X-ray Photon Detection and Energy Measurement

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- Data_Analysis_and_Filter_Optimization_for_Online_Pulse-Amplitude_Trieste_Nov_2025.pdf

Digital Pulse Processor: Main Functional Blocks - Part I

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Digital Pulse Processor: Main Functional Blocks - Part II

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Distribution of Certificates and Closing Remarks

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Edge AI Applications on FPGA-Based Systems

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Edge AI for the Internet of Things: Insights from Real-World Projects

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- ICTP-IAEA-School-Vukobratovic-Lec1-Monday.pdf

Embedded Linux on SoC-FPGA

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- 251105_EmbeddedLinux_fcastano.pdf

Embedded Real-Time Operating System

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End-to-End Dataset Generation for Machine Learning

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Fundamentals of Applied Machine Learning

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- 02--smr4110-2025-AppliedML.pdf

Green Intelligence at the Edge: Sustainable Hardware for AI

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Group Photo

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Group Photo

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Guide for Final Project - Part I

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Guide for Final Project - Part II

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Guide for Lab 1 - Getting Started with SoC

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Guide for Lab 2 - Reconfigurable Instrumentation on SoC-FPGA

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Guide for Lab 3 - SoC-FPGA Development Framework

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Guide for Lab 6: Pulse Acquisition and Detector Characterization

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Guide for Lab 7: Digital Pulse Processor (DPP)

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Handling High Event Rates and Pile-Up - Part I

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Handling High Event Rates and Pile-Up - Part II

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Hardware Description Language for Reconfigurable Instrumentation

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- Hardware_Description_Language_(HDL)_for_Reconfigurable_Instrumentation_.pdf

Hardware-Software Co-Design

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High Event-Rate Discrimination on Mixed Radiation Fields with Machine Learning

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- Morales_-_High_Event-Rate_Discrimination_on_Mixed_Radiation_Fields_with_ML.pdf

High-Level Synthesis (HLS) – Part I

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- HLS_Intro.pdf

High-Level Synthesis (HLS) – Part II

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Hog: An Open-Source Tool for Managing HDL Repositories on Git

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HyperFPGA: Heterogeneous Computing on MPSoC-FPGA at ICTP

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IAEA Programmes & NSIL Activities

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ICTP Programmes & MLab Activities

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- ICTP-Programmes-ML_Crespo.pdf

ICTP-IAEA MA-XRF Scanner

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Integrating Intelligence in 5G: How ML and AI Are Shaping 5G Networks?

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- ICTP-IAEA-School-Trieste-Lec3-Friday.pdf

Integrating Machine Learning into Digital Pulse Processing

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Introduction to AI-Enabled Semantic and Goal-Oriented Communications for the Internet of Things

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- ICTP-IAEA-School-Trieste-Lec2-Tuesday.pdf

Introduction to Machine Learning and Edge AI

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- 01--smr4110-2025-Intro-ML-Edge-AI.pdf

Lab 1 with tutors

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Lab 1 with tutors

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Lab 2 with tutors

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Lab 2 with tutors

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Lab 3 with tutors

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Lab 3 with tutors

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Lab 4.1: Training Machine Learning Models

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Lab 4.2: Applying Model Compression Techniques

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Lab 5.1: Integrating ML Models with HLS4ML for Hardware Synthesis

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Lab 5.2: Deploying Machine Learning Models on SoC-FPGA

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Lab 6 with tutors

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Lab 6 with tutors

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Lab 7 with tutors

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Lab 7 with tutors

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Model Optimization and Compression Techniques

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- 03--smr4110--ML-Compression.pdf

Opening Remarks

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Peripheral Interfaces & IP Integration

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- peripherals_interfaces_ip_integration.pdf

Programmable System on Chip (PSoC) Architecture

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- Programmable_System_on_Chip_PSoC_Architecture.pdf

Project Lab with Tutors

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Project Lab with tutors

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Project Lab with tutors

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Project lab with tutors

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Pulse Acquisition and Detector Characterization

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- SMR4100_Mladen_Bogovac_Pulse_Shaping.pdf

School Outline

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- smr4110-school_outline_2025-ML_Crespo.pdf

Semiconductors and Collaboration: Building Pathways for Innovation and Talent

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- Razaid_Hussin_ICTP.pdf

SoC: A Practical Implementation Overview on Intelligent Neurosystems

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- System_on_Chip_(SoC)_-_A_Practical_Implementation_on_Intelligent_Neurosystems-Sawal.pdf

The Open Standard RISC-V Architecture - Part I

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- RISC-V_the_open_standard.pdf

The Open Standard RISC-V Architecture - Part II

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Using FPGAs to Accelerate Machine Learning Algorithms

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- 04--smr4110-2025-hls4ml-Workflow.pdf

Virtual Machine and User Environment

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When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part I

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- WLMTC_-_Part_1.pdf

When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part II

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- WLMTC_-_Part_2.pdf

coffee-break

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coffee-break

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Organizers

Mladen Bogovac (IAEA, Austria), Maria Liz Crespo (ICTP, Italy), Kalliopi Kanaki (IAEA, Austria), Local Organiser: Maria Liz Crespo (ICTP)