Joint ICTP-IAEA School on Detector Signal Processing and Machine Learning for Scientific Instrumentation and Reconfigurable Computing | (smr 4110) (27 October 2025

Administration

Search

Search in Conferences:

Support

smr4110@ictp.it

Home > Contribution List

Contribution List

Displaying 77 contributions out of 77

Advanced SoC-FPGA Topics

Session:

- advanced_topics.pdf

C for Embedded Systems

Session:

- C_for_Embedded_Systems_2.pdf

Coffee Break

Session:

Coffee Break

Session:

Design Methodology for FPGA-based System on Chip

Session:

- design_methodology.pdf

Development Board: Zynq SoC

Session:

- Development_Board_Zynq_SoC_copy.pdf

Digital Pulse Processing for Isotope Identification

Session:

- SMR4100_Mladen_Bogovac_DPP_for_Isotope_Identification.pdf

Digital Pulse Processing for X-ray Photon Detection and Energy Measurement

Session:

- Data_Analysis_and_Filter_Optimization_for_Online_Pulse-Amplitude_Trieste_Nov_2025.pdf

Digital Pulse Processor: Main Functional Blocks - Part I

Session:

Digital Pulse Processor: Main Functional Blocks - Part II

Session:

Distribution of Certificates and Closing Remarks

Session:

Edge AI Applications on FPGA-Based Systems

Session:

Edge AI for the Internet of Things: Insights from Real-World Projects

Session:

- ICTP-IAEA-School-Vukobratovic-Lec1-Monday.pdf

Embedded Linux on SoC-FPGA

Session:

- 251105_EmbeddedLinux_fcastano.pdf

Embedded Real-Time Operating System

Session:

End-to-End Dataset Generation for Machine Learning

Session:

Fundamentals of Applied Machine Learning

Session:

- 02--smr4110-2025-AppliedML.pdf

Green Intelligence at the Edge: Sustainable Hardware for AI

Session:

Group Photo

Session:

Group Photo

Session:

Guide for Final Project - Part I

Session:

Guide for Final Project - Part II

Session:

Guide for Lab 1 - Getting Started with SoC

Session:

Guide for Lab 2 - Reconfigurable Instrumentation on SoC-FPGA

Session:

Guide for Lab 3 - SoC-FPGA Development Framework

Session:

Guide for Lab 6: Pulse Acquisition and Detector Characterization

Session:

Guide for Lab 7: Digital Pulse Processor (DPP)

Session:

Handling High Event Rates and Pile-Up - Part I

Session:

Handling High Event Rates and Pile-Up - Part II

Session:

Hardware Description Language for Reconfigurable Instrumentation

Session:

- Hardware_Description_Language_(HDL)_for_Reconfigurable_Instrumentation_.pdf

Hardware-Software Co-Design

Session:

High Event-Rate Discrimination on Mixed Radiation Fields with Machine Learning

Session:

- Morales_-_High_Event-Rate_Discrimination_on_Mixed_Radiation_Fields_with_ML.pdf

High-Level Synthesis (HLS) – Part I

Session:

- HLS_Intro.pdf

High-Level Synthesis (HLS) – Part II

Session:

Hog: An Open-Source Tool for Managing HDL Repositories on Git

Session:

HyperFPGA: Heterogeneous Computing on MPSoC-FPGA at ICTP

Session:

IAEA Programmes & NSIL Activities

Session:

ICTP Programmes & MLab Activities

Session:

- ICTP-Programmes-ML_Crespo.pdf

ICTP-IAEA MA-XRF Scanner

Session:

Integrating Intelligence in 5G: How ML and AI Are Shaping 5G Networks?

Session:

- ICTP-IAEA-School-Trieste-Lec3-Friday.pdf

Integrating Machine Learning into Digital Pulse Processing

Session:

Introduction to AI-Enabled Semantic and Goal-Oriented Communications for the Internet of Things

Session:

- ICTP-IAEA-School-Trieste-Lec2-Tuesday.pdf

Introduction to Machine Learning and Edge AI

Session:

- 01--smr4110-2025-Intro-ML-Edge-AI.pdf

Lab 1 with tutors

Session:

Lab 1 with tutors

Session:

Lab 2 with tutors

Session:

Lab 2 with tutors

Session:

Lab 3 with tutors

Session:

Lab 3 with tutors

Session:

Lab 4.1: Training Machine Learning Models

Session:

Lab 4.2: Applying Model Compression Techniques

Session:

Lab 5.1: Integrating ML Models with HLS4ML for Hardware Synthesis

Session:

Lab 5.2: Deploying Machine Learning Models on SoC-FPGA

Session:

Lab 6 with tutors

Session:

Lab 6 with tutors

Session:

Lab 7 with tutors

Session:

Lab 7 with tutors

Session:

Model Optimization and Compression Techniques

Session:

- 03--smr4110--ML-Compression.pdf

Opening Remarks

Session:

Peripheral Interfaces & IP Integration

Session:

- peripherals_interfaces_ip_integration.pdf

Programmable System on Chip (PSoC) Architecture

Session:

- Programmable_System_on_Chip_PSoC_Architecture.pdf

Project Lab with Tutors

Session:

Project Lab with tutors

Session:

Project Lab with tutors

Session:

Project lab with tutors

Session:

Pulse Acquisition and Detector Characterization

Session:

- SMR4100_Mladen_Bogovac_Pulse_Shaping.pdf

School Outline

Session:

- smr4110-school_outline_2025-ML_Crespo.pdf

Semiconductors and Collaboration: Building Pathways for Innovation and Talent

Session:

- Razaid_Hussin_ICTP.pdf

SoC: A Practical Implementation Overview on Intelligent Neurosystems

Session:

- System_on_Chip_(SoC)_-_A_Practical_Implementation_on_Intelligent_Neurosystems-Sawal.pdf

The Open Standard RISC-V Architecture - Part I

Session:

- RISC-V_the_open_standard.pdf

The Open Standard RISC-V Architecture - Part II

Session:

Using FPGAs to Accelerate Machine Learning Algorithms

Session:

- 04--smr4110-2025-hls4ml-Workflow.pdf

Virtual Machine and User Environment

Session:

When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part I

Session:

- WLMTC_-_Part_1.pdf

When Learning Meets the Channel: Edge AI through Split and Semantic Design – Part II

Session:

- WLMTC_-_Part_2.pdf

coffee-break

Session:

coffee-break

Session:

Organizers

Mladen Bogovac (IAEA, Austria), Maria Liz Crespo (ICTP, Italy), Kalliopi Kanaki (IAEA, Austria), Local Organiser: Maria Liz Crespo (ICTP)

Search

Support

Contribution List

Organizers

Co-sponsors