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Contribution List

Displaying 69 contributions out of 69
Session: Advanced Scientific Applications of FPGA
Session: Advanced Scientific Applications of FPGA 2
Session: Advanced Scientific Applications of FPGA 3
Session: Advanced Scientific Applications of FPGA 4
Session: Advanced Topics in Digital Signal Processing
Session: Advanced Topics in Digital Signal Processing2
Session: Applications in Digital Signal Processing
Session: Applications in Digital Signal Processing 2
Session: CMOS technology
Session: Combinational Logic Described in VHDL - Description, Synthesis and Simulation
Session: Combinational Logic Described in VHDL - Synthesis and Implementation
Session: Combinational Logic Described in VHDL - Synthesis and Implementation
Session: Combinational Logic Described in VHDL - Synthesis and Implementation
Session: Digital Design
Session: Digital Design - Combinatorial elements
Session: Digital Design - More complex elements: RAM, ROM, buses, pipeline concept, etc
Session: Digital Design - Sequential elements, Mealy and Moore FSM
Session: Digital Signal Processing
Session: Digital Signal Processing 2
Session: Digital Signal Processing 3
Session: Digital Signal Processing 4
Session: Digital Signal Processing 5
Session: Digital Signal Processing 6
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA
Session: Digital Signal Processing with FPGA. PMOD Modules (AD, DA, BNC). Design Example.
Session: Digital arithmetic - Basic arithmetic operations
Session: Digital arithmetic - Number representations
Session: FPGA Debugging
Session: FPGA Design Techniques
Session: FPGA Technology
Session: FPGA Timing and Tools for High Performance
Session: Hardware Description of FPGA Development Platform: Nexys 2
Session: ICTP RVI platform - Demo
Session: ISE WebPACK Design Software - Testbench - A Design Example
Session: Introduction to CMOS technology and VLSI Design
Session: Laboratory Overview
Session: Microelectronics at CERN
Session: Multidisciplinary Laboratory at ICTP
Session: OPENING CEREMONY
Session: Projects on RVI and DSP
Session: Projects on RVI and DSP
Session: Projects on RVI and DSP
Session: Projects on RVI and DSP
Session: REGISTRATION
Session: Reconfigurable Virtual Instrumentation (RVI) based on FPGA
Session: Sequential Logic Described in VHDL
Session: Sequential Logic Described in VHDL
Session: Sequential Logic Described in VHDL
Session: Sequential Logic Described in VHDL
Session: Sequential Logic Described in VHDL
Session: Sequential Logic Described in VHDL - A Design Example
Session: VHDL for FPGA Design
Session: VHDL for FPGA Design 2
Session: VHDL for FPGA Design 3
Session: VHDL for FPGA Design 4
Session: VHDL for FPGA Design 5
Session: VHDL for FPGA Design 6
Session: VHDL for FPGA Design 7
Session: VLSI Design
Session: Wishbone IP Interface Standard
Session: Wishbone IP Interface Standard 2

Organizers

Directors: L. Hernandez Tabares (Cuba) , N. Abdallah (USA), A. Cicuttin and M.L. Crespo (ICTP)