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Displaying
61
contributions
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61
AXI Bus and Custom IP Cores
Session:
Introduction_to_AXI_–_Custom_IP_C._SISTERNA.pdf
Academic Writing Strategy for Impacted Journal
Session:
Academic_Writing_Strategy_for_Impacted_Journal_M._M._B._I._REAZ.pdf
Brief introduction from participants
Session:
C for Embedded Systems
Session:
Embedded_‘C’_for_Zynq_C._SISTERNA.pdf
Distribution of Certificates and Closing Remarks
Session:
FPGA and System-on-Chip (SoC) technology
Session:
FPGA_and_System-on-Chip_(SoC)_technology_C.A._SISTERNA.pdf
FPGA for Accelerating Machine Learning Algorithms
Session:
FPGA_for_accelerating_machine_learning_algorithms_R._MOLINA.pdf
FPGAs and Quantum Computers
Session:
FPGAs computing just right thanks to application-specific arithmetic
Session:
FPGAs_computing_just_right_thanks_to_application-specific_arithmetic_F._DE_DINECHIN.pdf
FPGAs computing just right thanks to application-specific arithmetic
Session:
Computing_Just_Right-_Application-Specific_Arithmetic_with_FloPoCo_F._DINECHIN.pdf
FreeRTOS Tutorial
Session:
Fundamentals of VHDL (Hardware Description Language)
Session:
Gaining a Deeper Insight Into the Project Lab Setup - System and Hardware Perspective
Session:
Guide for Lab 1: Hello World + GPIO In/Out
Session:
Hello_World_and_GPIO_In_Out_R._MOLINA.pdf
Guide for Lab 2: ComBlock (RVI Communication Block)
Session:
The_RVI_communication_block-_ComBlock_M._BALLINA.pdf
Guide for Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
Session:
Guide for Lab 4: SoC-FPGA DAQ system and TCL
Session:
Lab4_MORALES_and_MOLINA.pdf
Guide for Project Lab 1.1: Pulse Acquisition and Detector Characterization
Session:
Guide for Project Lab 1.2: Digital Pulse Processing
Session:
Guide for Project Lab 2: Digital Pulse Processor (DPP)
Session:
HLS Demo
Session:
HLS_Demo_F._RINCON.pdf
Hardware and Software Interrupts on SoC
Session:
High Level Synthesis (HLS)
Session:
High-level_Synthesis_F._RINCON.pdf
HyperFPGA: Experimental Infrastructure for Reconfigurable Supercomputing
Session:
IAEA NSIL: Support to IAEA Member States and Recent Developments
Session:
NSIL_K._KANAKI.pdf
ICTP programmes and MLAB activities
Session:
ICTP_Programmes_and_MLAB_activities_M.L._CRESPO.pdf
Lab 1: Hello World + GPIO In/Out
Session:
Lab 2: ComBlock + RTL instantiation
Session:
Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
Session:
School_on_FPGA-based_SoC_Lab_3-_UDMA_A._SILVA.pdf
Lab 4: SoC-FPGA DAQ system and TCL
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
Lab activities with tutors
Session:
MLAB Visit
Session:
Opening Remarks
Session:
Project 1: Digital Pulse Processing for Isotope Identification
Session:
Introduction_to_Project_1.pdf
Project1_stage2.pdf
Project 2: Digital Pulse Processing for X-ray Photon Detection and Energy Measurement
Session:
Data_Analysis_and_Filter_Optimization_for_Online_Pulse-Amplitude_Measurement_A_Case_Study_on_High-Resolution_X-ray_Spectroscopy_A._CICUTTIN.pdf
Project Lab 1.2: Digital Pulse Processing
Session:
Project Lab 1.3: Baseline Restorer and Pile-Up Rejection
Session:
Real Time Operating System (FreeRTOS)
Session:
Experiment_DAQ_PmodAD1-1.pdf
Real_Time_Operating_System_(FreeRTOS)_H._RONGEN.pdf
Reconfigurable Virtual Instrumentation (RVI) based on SoC-FPGA
Session:
Reconfigurable_Virtual_Instrumentation_A._CICUTTIN.pdf
Registration formalities
Session:
School Outline
Session:
School_outline.pdf
Semiconductor Detectors, Fabrication Techniques, Quantum Detector Developments
Session:
Micro-_and_Nano-_Fabrication_&_Quantum_Technology-_Towards_Applications_R._HALL_WILTON.pdf
SoC Architecture and Design Methodology
Session:
SoC_Architecture_and_Design_Methodology_C.A._SISTERNA.pdf
SoC Architecture and Design Methodology
Session:
Switch Architectures for Data Center Networks
Session:
Switch_architectures_for_Data_Center_networks_P._CASTOLDI.pdf
The European Spallation Source Data Acquisition System
Session:
The_Detector_Data_Acquisition_System_of_the_European_Spallation_Source._R._WILTON.pdf
The FloPoCo arithmetic core generator
Session:
The Open Standard RISC-V Architecture
Session:
The_Open_Standard_RISC-V_Architecture_F._RINCON.pdf
The Role of Programmable Hardware Acceleration in Virtualized Communications Networks
Session:
The_Role_of_Programmable_Hardware_Acceleration_in_Virtualized_Communications_Networks_L._VALCARENGHI.pdf
Use of VMs and User environment
Session:
Use_of_VMs_and_User_environment_L.G._ORDONEZ.pdf
VHDL for Simulation
Session:
Verification_-__Test_Bench_C._SISTERNA.pdf
VHDL for Synthesis
Session:
HDL_for_Synthesis_C._SISTERNA.pdf
Zynq SoC: Evaluation and Development Board
Session:
Zynq_Evaluation_and_Development_Board_C._SISTERNA.pdf
Organizers
Maria Liz CRESPO (ICTP, Italy), Kalliopi KANAKI (IAEA, Austria), Mladen BOGOVAC (IAEA, Austria), Andres CICUTTIN (ICTP, Italy), Local Organiser: Maria Liz Crespo (ICTP)
Co-sponsors