Joint ICTP-IAEA School on Systems-on-Chip Based on FPGA for Scientific Instrumentation and Reconfigurable Computing | (smr 3891) (20 November 2023 - 1 December 2023)

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Contribution List

Displaying 61 contributions out of 61

AXI Bus and Custom IP Cores

Session:

- Introduction_to_AXI_–_Custom_IP_C._SISTERNA.pdf

Academic Writing Strategy for Impacted Journal

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- Academic_Writing_Strategy_for_Impacted_Journal_M._M._B._I._REAZ.pdf

Brief introduction from participants

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C for Embedded Systems

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- Embedded_‘C’_for_Zynq_C._SISTERNA.pdf

Distribution of Certificates and Closing Remarks

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FPGA and System-on-Chip (SoC) technology

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- FPGA_and_System-on-Chip_(SoC)_technology_C.A._SISTERNA.pdf

FPGA for Accelerating Machine Learning Algorithms

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- FPGA_for_accelerating_machine_learning_algorithms_R._MOLINA.pdf

FPGAs and Quantum Computers

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FPGAs computing just right thanks to application-specific arithmetic

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- FPGAs_computing_just_right_thanks_to_application-specific_arithmetic_F._DE_DINECHIN.pdf

FPGAs computing just right thanks to application-specific arithmetic

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- Computing_Just_Right-_Application-Specific_Arithmetic_with_FloPoCo_F._DINECHIN.pdf

FreeRTOS Tutorial

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Fundamentals of VHDL (Hardware Description Language)

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Gaining a Deeper Insight Into the Project Lab Setup - System and Hardware Perspective

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Guide for Lab 1: Hello World + GPIO In/Out

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- Hello_World_and_GPIO_In_Out_R._MOLINA.pdf

Guide for Lab 2: ComBlock (RVI Communication Block)

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- The_RVI_communication_block-_ComBlock_M._BALLINA.pdf

Guide for Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook

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Guide for Lab 4: SoC-FPGA DAQ system and TCL

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- Lab4_MORALES_and_MOLINA.pdf

Guide for Project Lab 1.1: Pulse Acquisition and Detector Characterization

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Guide for Project Lab 1.2: Digital Pulse Processing

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Guide for Project Lab 2: Digital Pulse Processor (DPP)

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HLS Demo

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- HLS_Demo_F._RINCON.pdf

Hardware and Software Interrupts on SoC

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High Level Synthesis (HLS)

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- High-level_Synthesis_F._RINCON.pdf

HyperFPGA: Experimental Infrastructure for Reconfigurable Supercomputing

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IAEA NSIL: Support to IAEA Member States and Recent Developments

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- NSIL_K._KANAKI.pdf

ICTP programmes and MLAB activities

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- ICTP_Programmes_and_MLAB_activities_M.L._CRESPO.pdf

Lab 1: Hello World + GPIO In/Out

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Lab 2: ComBlock + RTL instantiation

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Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook

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- School_on_FPGA-based_SoC_Lab_3-_UDMA_A._SILVA.pdf

Lab 4: SoC-FPGA DAQ system and TCL

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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Lab activities with tutors

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MLAB Visit

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Opening Remarks

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Project 1: Digital Pulse Processing for Isotope Identification

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- Introduction_to_Project_1.pdf
- Project1_stage2.pdf

Project 2: Digital Pulse Processing for X-ray Photon Detection and Energy Measurement

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- Data_Analysis_and_Filter_Optimization_for_Online_Pulse-Amplitude_Measurement_A_Case_Study_on_High-Resolution_X-ray_Spectroscopy_A._CICUTTIN.pdf

Project Lab 1.2: Digital Pulse Processing

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Project Lab 1.3: Baseline Restorer and Pile-Up Rejection

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Real Time Operating System (FreeRTOS)

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- Experiment_DAQ_PmodAD1-1.pdf
- Real_Time_Operating_System_(FreeRTOS)_H._RONGEN.pdf

Reconfigurable Virtual Instrumentation (RVI) based on SoC-FPGA

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- Reconfigurable_Virtual_Instrumentation_A._CICUTTIN.pdf

Registration formalities

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School Outline

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- School_outline.pdf

Semiconductor Detectors, Fabrication Techniques, Quantum Detector Developments

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- Micro-_and_Nano-_Fabrication_&_Quantum_Technology-_Towards_Applications_R._HALL_WILTON.pdf

SoC Architecture and Design Methodology

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- SoC_Architecture_and_Design_Methodology_C.A._SISTERNA.pdf

SoC Architecture and Design Methodology

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Switch Architectures for Data Center Networks

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- Switch_architectures_for_Data_Center_networks_P._CASTOLDI.pdf

The European Spallation Source Data Acquisition System

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- The_Detector_Data_Acquisition_System_of_the_European_Spallation_Source._R._WILTON.pdf

The FloPoCo arithmetic core generator

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The Open Standard RISC-V Architecture

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- The_Open_Standard_RISC-V_Architecture_F._RINCON.pdf

The Role of Programmable Hardware Acceleration in Virtualized Communications Networks

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- The_Role_of_Programmable_Hardware_Acceleration_in_Virtualized_Communications_Networks_L._VALCARENGHI.pdf

Use of VMs and User environment

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- Use_of_VMs_and_User_environment_L.G._ORDONEZ.pdf

VHDL for Simulation

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- Verification_-__Test_Bench_C._SISTERNA.pdf

VHDL for Synthesis

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- HDL_for_Synthesis_C._SISTERNA.pdf

Zynq SoC: Evaluation and Development Board

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- Zynq_Evaluation_and_Development_Board_C._SISTERNA.pdf

Organizers

Maria Liz CRESPO (ICTP, Italy), Kalliopi KANAKI (IAEA, Austria), Mladen BOGOVAC (IAEA, Austria), Andres CICUTTIN (ICTP, Italy), Local Organiser: Maria Liz Crespo (ICTP)

Co-sponsors

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