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Displaying 23 speakers out of 23
AGUSTIN SILVA (National University of Mar del Plata, Argentina)
FPGAs and Quantum Computers
ANDRES CICUTTIN (ICTP, Italy)
Reconfigurable Virtual Instrumentation (RVI) based on SoC-FPGA
Project 2: Digital Pulse Processing for X-ray Photon Detection and Energy Measurement
BRUNO VALINOTI (ICTP, Italy)
Guide for Project Lab 2: Digital Pulse Processor (DPP)
CRISTIAN ALEJANDRO SISTERNA (Universidad Nacional de San Juan, Argentina)
FPGA and System-on-Chip (SoC) technology
SoC Architecture and Design Methodology
SoC Architecture and Design Methodology
C for Embedded Systems
Hardware and Software Interrupts on SoC
AXI Bus and Custom IP Cores
Fundamentals of VHDL (Hardware Description Language)
VHDL for Synthesis
VHDL for Simulation
CRISTIAN ALEJANDRO SISTERNA (Universidad Nacional de San Juan, Argentina)
Zynq SoC: Evaluation and Development Board
FERNANDO RINCON CALLE (University of Castilla-La Mancha, Spain)
The Open Standard RISC-V Architecture
High Level Synthesis (HLS)
HLS Demo
FLORENT MARIE PAUL DUPONT DE DINECHIN (National Institut of Applied Sciences, France)
FPGAs computing just right thanks to application-specific arithmetic
FPGAs computing just right thanks to application-specific arithmetic
The FloPoCo arithmetic core generator
GIOVANNI BALLINA ESCOBAR (ICTP, Italy)
Guide for Lab 2: ComBlock (RVI Communication Block)
HEINRICH BARTHOLOMAUS RONGEN (Juelich Gmbh, Germany)
Real Time Operating System (FreeRTOS)
FreeRTOS Tutorial
IVAN MORALES ARGUETA (ICTP, Italy)
Guide for Lab 4: SoC-FPGA DAQ system and TCL
Guide for Project Lab 1.1: Pulse Acquisition and Detector Characterization
Guide for Project Lab 1.2: Digital Pulse Processing
KALLIOPI KANAKI (IAEA, Austria)
IAEA NSIL: Support to IAEA Member States and Recent Developments
LAB TUTORS
Lab 1: Hello World + GPIO In/Out
Lab 2: ComBlock + RTL instantiation
Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
Lab 4: SoC-FPGA DAQ system and TCL
Lab activities with tutors
Lab activities with tutors
Lab activities with tutors
Lab activities with tutors
Lab activities with tutors
LUCA VALCARENGHI (Scuola Superiore Sant'Anna, Italy)
The Role of Programmable Hardware Acceleration in Virtualized Communications Networks
LUIS GUILLERMO GARCÍA ORDÓÑEZ (ICTP, Italy)
Use of VMs and User environment
MARIA LIZ CRESPO (ICTP, Italy)
School Outline
ICTP programmes and MLAB activities
MARIA LIZ CRESPO (ICTP, ITALY), ANDRES CICUTTIN (ICTP, ITALY)
Opening Remarks
MD MAMUN BIN IBNE REAZ (Independent University Bangladesh)
Academic Writing Strategy for Impacted Journal
MLADEN BOGOVAC (IAEA, Austria)
Project 1: Digital Pulse Processing for Isotope Identification
Project Lab 1.2: Digital Pulse Processing
Project Lab 1.3: Baseline Restorer and Pile-Up Rejection
NIKOLA JOVALEKIC (Teledyne DALSA High Tech, The Netherlands)
Gaining a Deeper Insight Into the Project Lab Setup - System and Hardware Perspective
PIERO CASTOLDI (Scuola Superiore Sant'Anna, Italy)
Switch Architectures for Data Center Networks
RICHARD HALL-WILTON (Bruno Kessler Foundation, Italy)
The European Spallation Source Data Acquisition System
Semiconductor Detectors, Fabrication Techniques, Quantum Detector Developments
ROMINA SOLEDAD MOLINA (ICTP, Italy)
Guide for Lab 1: Hello World + GPIO In/Out
FPGA for Accelerating Machine Learning Algorithms
WERNER FLORIAN (ICTP, Italy)
Guide for Lab 3: SoC-FPGA Development Framework: UDMA & Jupyter Notebook
HyperFPGA: Experimental Infrastructure for Reconfigurable Supercomputing

Organizers

Maria Liz CRESPO (ICTP, Italy), Kalliopi KANAKI (IAEA, Austria), Mladen BOGOVAC (IAEA, Austria), Andres CICUTTIN (ICTP, Italy), Local Organiser: Maria Liz Crespo (ICTP)

Co-sponsors